Search - vhdl can

Search - vhdl can - List

[VHDL-FPGA-Verilog] vhdl-多功能电子表 DL : 0: 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Update : 2025-02-17 Size : 5kb Publisher : 王继东
[VHDL-FPGA-Verilog] 8位数字频率计 DL : 0: 数字频率计~ VHDL 实现可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
Update : 2025-02-17 Size : 642kb Publisher : 熊明
[VHDL-FPGA-Verilog] VHDL语言100例详解 DL : 0: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Update : 2025-02-17 Size : 6.33mb Publisher : 穆群生
[VHDL-FPGA-Verilog] 国外的VHDL应用例子 DL : 0: 国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!
Update : 2025-02-17 Size : 227kb Publisher : gjd
[VHDL-FPGA-Verilog] VHDL例程 DL : 0: 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看-lot of routines, to learn VHDL programming of great help, I can not see
Update : 2025-02-17 Size : 165kb Publisher : 周
[VHDL-FPGA-Verilog] VHDL程序范例 DL : 0: 这是有关VHDL的一些范例，可以通过范例学习一点东西，巩固自己学过的东西-This is the VHDL some examples, examples can learn something consolidate learned things
Update : 2025-02-17 Size : 5kb Publisher : 刘建
[VHDL-FPGA-Verilog] vhdl对数 DL : 0: 对数计算源程序，能够在FPGA中计算某数的对数，VHDL源代码，-right calculating source, the FPGA can be calculated for a number of a few, VHDL source code,
Update : 2025-02-17 Size : 114kb Publisher : wl
[VHDL-FPGA-Verilog] CK20-VHDL DL : 0: 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
Update : 2025-02-17 Size : 4kb Publisher : 林海
[VHDL-FPGA-Verilog] hamming_decoder DL : 0: 汉明编码和解码的VHDL程序，直接解压就可以了-Hamming encoding and decoding process of VHDL, can be directly extracted a
Update : 2025-02-17 Size : 1kb Publisher : 李成军
[VHDL-FPGA-Verilog] SONGER DL : 0: 基于FPGA的VHDL可以产生不同的音调,象音乐一样-based FPGA VHDL can produce different tones, like the same music
Update : 2025-02-17 Size : 1kb Publisher : 相耀
[Books] VHDL-beststudy DL : 0: This a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). You may use this booklet for your own personal learning purposes. You may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these conditions, contact me and we can come to some arrangement. -This a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%). You may use this boo klet for your own personal learning purposes. Y ou may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these co nditions. contact me and we can come to some arrangement.
Update : 2025-02-17 Size : 240kb Publisher : 罗春晖
[Linux-Unix] erc32vhdl-1.0.tar DL : 0: ERC32 经典的sparc v7 cpu，针对嵌入式应用，欧洲宇航局采用VHDL语言，可综合。-ERC32 classic sparc v7 cpu against embedded applications, European Space using VHDL can be integrated.
Update : 2025-02-17 Size : 383kb Publisher : wangfeng
[File Format] VHDL_clock DL : 0: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Update : 2025-02-17 Size : 103kb Publisher : lianbin
[VHDL-FPGA-Verilog] vhdl-examples DL : 0: 这是eda初学者可以借鉴的两个关于电子频率计的VHDL设计实例-This is the EDA beginners can learn from two of electronic Cymometer VHDL Design Example
Update : 2025-02-17 Size : 11kb Publisher : 刘磊
[VHDL-FPGA-Verilog] VHDL-six DL : 0: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Update : 2025-02-17 Size : 25kb Publisher : philohb
[VHDL-FPGA-Verilog] can DL : 0: can IP CORE .VERY GOOD AS A STUDY FILE-can IP CORE. VERY GOOD AS A STUDY FILE
Update : 2025-02-17 Size : 96kb Publisher : lijun
[VHDL-FPGA-Verilog] can.tar DL : 0: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Update : 2025-02-17 Size : 53kb Publisher : yu
[VHDL-FPGA-Verilog] can DL : 0: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Update : 2025-02-17 Size : 87kb Publisher : 戴求淼
[VHDL-FPGA-Verilog] a-vhdl-can-controller DL : 0: a vhdl can controller project using vhdl programmming language-a vhdl can controller project using vhdl programmming language..
Update : 2025-02-17 Size : 110kb Publisher : Rahul
[VHDL-FPGA-Verilog] VHDL DL : 0: 各种基本的VHDL实例，可以用来参考学习，希望能够帮到大家！-Examples of the basic VHDL can be used to refer to learning, want to help everyone!
Update : 2025-02-17 Size : 6.03mb Publisher : 吴斌

« 12 3 4 5 6 7 8 9 10 ... 50 »