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[2D Graphic] XLIB

Description: 2D图像滤波VHDL代码。 2D图像滤波VHDL代码。-2D image filtering VHDL code. 2D image filtering VHDL code. 2D image filtering VHDL code.
Platform: | Size: 13312 | Author: leisuee | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码 附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[assembly language] ADC_Contrl

Description: 心电采集中A/D的代码，需要的可以参考一下-ECG acquisition A/D code, needed for reference
Platform: | Size: 4096 | Author: 黄建 | Hits:

[Crack Hack] CRC

Description: 通过对于模2除法的研究 可以得到如下方法： 1． 把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。 2． 在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。 3． 如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。 4． 把滑块变量d往后滑动一位。 5． 循环步骤（3，4）11次。 6． 执行步骤3。 7． 得到余数c，把c转成信号输出。 -Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal.
Platform: | Size: 6144 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] bhgfdti

Description: 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step addition and subtraction counter
Platform: | Size: 423936 | Author: 俞皓尹 | Hits:

[Other] VHDLcodeforaDFlipFlop

Description: vhdl code for D flip flop counter
Platform: | Size: 13312 | Author: SANTOSH | Hits:

[Crack Hack] rsa

Description: 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
Platform: | Size: 2384896 | Author: 齐娜 | Hits:

[Windows Develop] Sequencedetector

Description: 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the pulse sequence signal, which is a broad field of digital communication applications. When the detector continuously received after a group of serial binary code, if this group of pre-code and the code detector in the same output as A, otherwise the output B. Sequence detection I/O port design are as follows: Let Din is the serial data input, clk is work the clock, clr is a reset signal, D is the 8-bit preset number to be detected, QQ is the test results output.
Platform: | Size: 4096 | Author: yufang | Hits:

[VHDL-FPGA-Verilog] JPEG2000

Description: 用于JPEG2000的53小波VHDL源码-53 for the JPEG2000 wavelet VHDL source code
Platform: | Size: 1024 | Author: 闫霜山 | Hits:

[VHDL-FPGA-Verilog] srandDflipflop

Description: this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 205824 | Author: jatab | Hits:

[mpeg mp3] mpeg2_idct_hw

Description: 2-D的DCT/IDCT在軟硬體上的verilog code-dct/idct source code for soc
Platform: | Size: 10801152 | Author: 陳伯綸 | Hits:

[VHDL-FPGA-Verilog] Realization_of_FPGA_for_LDPC_encoding

Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC code．
Platform: | Size: 165888 | Author: 秦小星 | Hits:

[Internet-Network] vhdlcode

Description: Vhdl code for d flip flop
Platform: | Size: 9216 | Author: Ajay Kumar | Hits:

[VHDL-FPGA-Verilog] VHDL-Code-For-BCD-To-Excess3--Code-Converter-By-D

Description: VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling-VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling
Platform: | Size: 38912 | Author: rik | Hits:

[VHDL-FPGA-Verilog] johncounter_D

Description: VHDL CODE FOR JOHNSON COUNTER USING D FLIPFLOP
Platform: | Size: 592896 | Author: pinky | Hits:

[Other] ads1675

Description: 通过FPGA读取24Bit的A/D芯片ADS1675的VHDL代码程序-VHDL Code for 24 bits ad1675
Platform: | Size: 5120 | Author: zhou | Hits:

[VHDL-FPGA-Verilog] d_flip_en

Description: VHDL code for generating D-flip flop
Platform: | Size: 467968 | Author: mohamed | Hits:

[Education soft system] ReadWrite-RAM-VHDL-source-code

Description: This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic
Platform: | Size: 1024 | Author: ss | Hits:

[ELanguage] encoder

Description: VHDL Code for D-Flip Flop & Matching Unit
Platform: | Size: 4096 | Author: Mohammed Ismail | Hits:

[GPS develop] rs-code

Description: VHDL Code for D-Flip Flop & Matching Unit
Platform: | Size: 16384 | Author: Mohammed Ismail | Hits:
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