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Description: DW 256 DUP(?) STACK1 ENDS DDATA SEGMENT MES1 DB The least number is:$ MES2 DB 0AH,0DH, The largest number is:$ NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H DDATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DDATA START: MOV AX,DDATA MOV DS,AX MOV SI,OFFSET NUMB MOV CX,0008H JCXZ A4 MOV BH,[SI] MOV BL,BH A1: LODSB AL=DS:[SI],SI=SI+1 CMP AL,BH JBE A2 MOV BH,AL JMP A3 A2: CMP AL,BL JAE A3 MOV BL,AL A3: LOOP A1 A4: MOV DX,OFFSET MES1 show mes1 MOV AH,09H INT 21H MOV AL,BL show the least number AND AL,0F0H get the highest 4 bits SHR AL,4 CMP AL,0AH JB C2 ADD AL,07H C2: ADD AL,30H MOV DL,AL show character MOV AH,02H INT 21H MOV AL,BL AND AL,0FH get the lowest 4 bits CMP AL,0AH JB C3 ADD AL,07H C3: ADD AL,30H MOV DL,AL show character MOV AH,02H INT 21H MOV DX,OFFSET MES2 show mes2 MOV AH,09H INT 21H -DW 256 DUP (?) STACK1 ENDSDDATA SEGMENTMES1 DB The least number is: $ MES2 DB 0AH, 0DH, The largest number is: $ NUMB DB 0D9H, 07H, 8BH, 0C5H, 0EBH, 04H, 9DH, 0F9HDDATA ENDSCODE SEGMENT ASSUME CS: CODE, DS: DDATASTART: MOV AX, DDATA MOV DS, AX MOV SI, OFFSET NUMB MOV CX, 0008H JCXZ A4 MOV BH, [SI] MOV BL, BHA1: LODSB AL = DS: [SI], SI = SI+ 1 CMP AL, BH JBE A2 MOV BH, AL JMP A3A2: CMP AL, BL JAE A3 MOV BL, ALA3: LOOP A1A4: MOV DX, OFFSET MES1 show mes1 MOV AH, 09H INT 21H MOV AL, BL show the least number AND AL , 0F0H get the highest 4 bits SHR AL, 4 CMP AL, 0AH JB C2 ADD AL, 07H C2: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV AL, BL AND AL, 0FH get the lowest 4 bits CMP AL, 0AH JB C3 ADD AL, 07HC3: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV DX, OFFSET MES2 show mes2 MOV AH, 09H INT 21H
Platform: | Size: 1024 | Author: 张于 | Hits:

[VHDL-FPGA-VerilogWIRELESS

Description: This file contains source code for DS-CDMA transciver using VHDL. it is having two source codes one is for Transmitter and another is for reciever programme.
Platform: | Size: 4096 | Author: RUPA KRISHNA | Hits:

[VHDL-FPGA-Verilogcdma

Description: vhdl code for flip-flop,lfsr
Platform: | Size: 104448 | Author: sandeep | Hits:

[VHDL-FPGA-Verilogbpsk_spread_spectrum_modulator_demodulator

Description: code for bpsk spread spectrum modulator used in cdma -code for bpsk spread spectrum modulator used in cdma ..
Platform: | Size: 8192 | Author: ANIL | Hits:

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