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[VHDL-FPGA-Verilogdivision_cordic

Description: verilog code for division based on cordic algorithm
Platform: | Size: 1024 | Author: meysam | Hits:

[VHDL-FPGA-Verilogcode

Description: 本源码是基于VHDL语言环境下的基础实验源码,共分七个部分。分别是:序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
Platform: | Size: 20480 | Author: 朱召宇 | Hits:

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