Description: 10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。-10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on. Platform: |
Size: 41984 |
Author:petri |
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Description: 低密度奇偶校验码的VHDL程序，用于LDPC码的硬件实现-LDPC code VHDL program for the LDPC code of hardware implementation Platform: |
Size: 2048 |
Author:赵天婵 |
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Description: LDPC 编码的Verilog源代码，我没有验证，不知道效果如何，与大家分享，供大家参考。-LDPC-coded Verilog source code, I did not verify, I do not know how to share with you, for your reference. Platform: |
Size: 622592 |
Author:peter |
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Description: the attached file consists of LDPC code (7,3).
this code can be easily implemented on fpga kit(sparten-3) Platform: |
Size: 2048 |
Author:babi |
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Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC
cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of
codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device
for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is
implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC
code． Platform: |
Size: 165888 |
Author:秦小星 |
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Search - vhdl code for ldpc