Search - vhdl code for traffic light control

[VHDL-FPGA-Verilog] DEMO22

Description: ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ　环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
Platform: | Size: 598016 | Author: liu | Hits:

Description: 开源的串口通信程序，用vhdl 编写的，已通过测试，在DE2的开发板上能够运行。-Open source serial communication procedures, prepared by using VHDL, has been tested in the DE2 development board to run.
Platform: | Size: 2048 | Author: caijl88 | Hits:

[VHDL-FPGA-Verilog] jtd

Description: 本实验要完成任务就是设计一个简单的交通灯控制器，交通灯显示用实验箱的交通灯模块和七段码管中的任意两个来显示。系统时钟选择时钟模块的1KHz 时钟，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz 脉冲，即每1s 中递减一次，在显示时间小于3 秒的时候，通车方向的黄灯以2Hz的频率闪烁。系统中用S1 按键进行复位。-To complete the tasks in this experiment is to design a simple traffic light controller, traffic lights display box with the experimental traffic lights control module and the seventh of arbitrary code to display the two. Select system clock clock module 1KHz clock, clock called for blinking yellow light 2Hz, and seventh time code display tube for 1Hz pulse, that is diminishing every 1s in time, display time in less than three seconds when the opening direction of the yellow flicker frequency to 2Hz. System used for reset button S1.
Platform: | Size: 41984 | Author: 卢陶 | Hits:

[VHDL-FPGA-Verilog] trafficled

Description: 数字电路的交通灯设计，具有主道和旁道两个不同时间的控制处理，使用vhdl语言编译，附有完整的报告及代码，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design of a traffic light with a main road and bypass roads are two different time control processing, using vhdl language compiler, with full report and code.
Platform: | Size: 2599936 | Author: xiaoyao9933 | Hits:

[VHDL-FPGA-Verilog] traffic-light

Description: 使用VHDL编写的交通灯控制代码，可以用于课程设计或者毕业设计使用，已经经过调试运行正确-Using the VHDL code written in traffic light control, can be used for graduate design course design or use, has been commissioning the right
Platform: | Size: 1808384 | Author: 王战雷 | Hits:

[VHDL-FPGA-Verilog] Trafficlightcontrol

Description: VHDL code for traffic light control
Platform: | Size: 4096 | Author: qqq | Hits:

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[VHDL-FPGA-Verilog] DEMO22

[Com Port] uart

[VHDL-FPGA-Verilog] jtd

[VHDL-FPGA-Verilog] trafficled

[VHDL-FPGA-Verilog] traffic-light

[VHDL-FPGA-Verilog] Trafficlightcontrol

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