Description: 本代码用于产生FPGA内部的一个200Mhz的时钟，使得内部信号在此时钟下同步工作-The code used to generate a 200Mhz internal FPGA clock, the internal clock signal in this work under the synchronous Platform: |
Size: 2048 |
Author:yang |
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Description: 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA.
(1) Synthesize and verify (simulate) the VHDL design of the FIFOs
(2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells) and PTs (product terms) are needed? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.
(3) For FPGA implementation (place and route) of the FIFOs, how many LBs (logic blocks)? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.
(4) Try to synthesize again the design with timing constraints and compare with its former counterparts. You will create the timing constraint file by yourself and add it to your project. Please refer to the following graphic interface of ISE:
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Size: 115712 |
Author:魏攸 |
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Search - vhdl code internal clock fpga