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[SourceCode] altera sdram controller

Description: altera sdram controller vhdl
Platform: | Size: 2365413 | Author: langzhongfeilang@126.com | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031168 | Author: 包盛花 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] pci 的vhdl 源代码

Description: pci 的vhdl 源代码-The source code of PCI VHDL.
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] I2C总线控制器 altera提供-VHDL

Description: I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
Platform: | Size: 1639424 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2458624 | Author: 陈东平 | Hits:

[VHDL-FPGA-Verilog] USB控制器VHDL程序

Description: USB控制器VHDL程（usb_xilinx_vhdl）,用XILINX公司的FPGA实现-VHDL-USB controller (usb_xilinx_vhdl) XILINX FPGA
Platform: | Size: 60416 | Author: 夏社 | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437248 | Author: kevin | Hits:

[Documents] SDRAM-VHDL

Description: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Platform: | Size: 124928 | Author: | Hits:

[VHDL-FPGA-Verilog] ads7844

Description: 本源码介绍了ADS7844 AD转换芯片的VHDL控制器。-The source of the introduction ADS7844 AD conversion of the VHDL controller chip.
Platform: | Size: 1386496 | Author: 周生 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 标准SDR SDRAM控制器参考设计_verilog_lattice\sdr_ctrl.v-Standard SDR SDRAM Controller Reference Design _verilog_latticesdr_ctrl.v
Platform: | Size: 776192 | Author: 王廷龙 | Hits:

[VHDL-FPGA-Verilog] DPRAM

Description: 利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
Platform: | Size: 1024 | Author: 孙敬辉 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
Platform: | Size: 3072 | Author: 张楚荀 | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Platform: | Size: 1031168 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
Platform: | Size: 1013760 | Author: wfs | Hits:

[File Format] vhdl

Description: 电梯控制器的模块电路，其中一个很重要的模块，是txt格式的代码-Elevator controller module circuit, which is a very important module is the code txt format
Platform: | Size: 1024 | Author: yang | Hits:

[VHDL-FPGA-Verilog] EDA-elevator-controller

Description: 在QuartusII里用VHDL仿真实现电梯控制器-QuartusII elevator controller VHDL Simulation
Platform: | Size: 404480 | Author: Yolanda | Hits:

[Embeded-SCM Develop] plx9054-localbus-cpld-vhdl-src

Description: PLX 公司 PLX9054 pci target controller local bus interface vhdl programe-PLX inc. PLX9054 pci target controller local bus interface vhdl programe
Platform: | Size: 1024 | Author: richardz | Hits:

[VHDL-FPGA-Verilog] lift

Description: （1）用VHDL实现四层电梯运行控制器。 （2）电梯运行锁用一按钮代替（开锁上电），低电平可以运行，高电平不能运行。 （3）每层电梯入口处设有上行、下行请求按钮，电梯内设有乘客到达层次的停站要求开关，高电平有效。 （4）有电梯所处楼层指示灯和电梯上行、下行状态指示灯。 （5）电梯到达某一层时，该层指示灯亮，并一直保持到电梯到达另一层为止。电梯上行或下行时，相应状态指示灯亮。 （6）电梯接收到停站请求后，每层运行2秒，到达停站层，停留2秒后门自动打开，开门指示灯亮，开门6秒后电梯自动关门。 （7）能记忆电梯内、外的请求信号，并按照电梯的运行规则依次响应，请求信号保留至响应后撤除。 （8）人数超载或超重用一按钮代替，高电平有效，超载时电梯不能运行，并有相应指示。 （9）事故报警按钮高电平有效，事故报警不能运行，并有指示灯，信号保留至事故消除 -(1) the realization of four-storey elevator with VHDL controller operation. (2) elevator button with a lock to run in place of (unlock power), low run, can not run high. (3) on each floor with elevator at the entrance to the uplink, downlink request button, which are equipped with passenger elevators to reach the level of the requirements of stoppings switch, high effective. (4) elevators and escalators which lights up the floor, down the state indicator. (5) elevator to reach a certain level, the level indicator light, and has remained until the elevator arrived at another level. Elevator uplink or downlink, the corresponding status indicator light. (6) Elevator stops receiving a request, each running two seconds to reach the stops layer, two seconds back door stay open automatically, open the door indicator light, 6 seconds after the elevator door closed automatically. (7) to memory elevator inside and outside the request signal, and in accordance with the rules followed
Platform: | Size: 289792 | Author: 管皮皮 | Hits:
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