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[VHDL-FPGA-Verilog] VHDL.sheji.2 DL : 0: 电子时钟VHDL程序与仿真 10进制计数器设计与仿真 6进制计数器设计与仿真-electronic clock procedures and VHDL simulation Decimal counter design and simulation of six NUMBER Design and Simulation
Update : 2025-02-17 Size : 58kb Publisher : 少龙
[VHDL-FPGA-Verilog] counter1 DL : 0: vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it
Update : 2025-02-17 Size : 1kb Publisher : 张三
[VHDL-FPGA-Verilog] conter1 DL : 0: 一个VHDL计数器。可进一步改装成实际的计数器使用-a VHDL counter. Can be further converted into actual use of the Counter
Update : 2025-02-17 Size : 1kb Publisher : z9z9
[VHDL-FPGA-Verilog] N_counter_VHDL DL : 0: 任意N进制分频器的标准VHDL代码（原创）-arbitrary N divider 229 standard VHDL code (original)
Update : 2025-02-17 Size : 1kb Publisher : 汤维
[VHDL-FPGA-Verilog] vhdlgenerateofsentencegrammarapplication DL : 0: vhdl实验计数器：generate语句的应用-Experimental VHDL Counter: generate statement application
Update : 2025-02-17 Size : 1kb Publisher : 王天辉
[VHDL-FPGA-Verilog] counter DL : 0: VHDL计数器的TestBench，适合初学者-VHDL counter TestBench, suitable for beginners
Update : 2025-02-17 Size : 1kb Publisher : hbsun
[VHDL-FPGA-Verilog] COUNT10 DL : 0: 一个十进制计数器的vhdl程序，大家可以参考，已经经过编译了-A decimal counter VHDL process, everyone can refer to, has been compiled
Update : 2025-02-17 Size : 106kb Publisher : wangyan
[VHDL-FPGA-Verilog] counter DL : 0: 计数器的VHDL设计，已经在FPGA上验证-VHDL counter design, has been tested in the FPGA
Update : 2025-02-17 Size : 1kb Publisher : chen
[VHDL-FPGA-Verilog] d02 DL : 0: 此程序为脉宽测量电路vhdl代码，能够对输入的脉冲信号用10HZ时钟进行计数，输出计数结果。主模块调用显示、计数、控制三个模块实现主体功能-This procedure for pulse width measurement circuit VHDL code, able to input the pulse signal with 10Hz clock count, the output result of the calculation. Main module calls show that counts, control the main functions of the three modules realize
Update : 2025-02-17 Size : 2kb Publisher : jingken
[VHDL-FPGA-Verilog] VHDL DL : 0: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Update : 2025-02-17 Size : 880kb Publisher : 李帆
[MiddleWare] counter_4_bit DL : 0: 非常有参考价值的计数器源代码，用到了许多的编写程序的技巧，可以借鉴-Very useful counter source code, used in many programming skills, can learn from
Update : 2025-02-17 Size : 83kb Publisher : 胡容华
[VHDL-FPGA-Verilog] VHDL DL : 0: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Update : 2025-02-17 Size : 37kb Publisher : 袁玉佳
[Software Engineering] VHDL DL : 0: 在电子技术中，频率是最基本的参数之一，又与许多电参量的测量方案、测量结果都有十分密切的关系，因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速，以及便于实现测量过程自动化等优点，是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计，并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门，通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率，最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求，而且具有了单片机的稳定性和成熟性，且控制能力强，是一种低成本，高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Update : 2025-02-17 Size : 215kb Publisher : 张林锋
[File Format] VHDL DL : 0: eda课程，包括数码管显示，可变步长计数器的编写-eda courses, including digital display, variable-step preparation of counter
Update : 2025-02-17 Size : 376kb Publisher : lxc
[VHDL-FPGA-Verilog] VHDL16bitcouner DL : 0: 利用VHDL编写的一个简单的16位计数器-VHDL prepared using a simple 16-bit counter
Update : 2025-02-17 Size : 175kb Publisher : jian
[VHDL-FPGA-Verilog] counter DL : 0: 适用于FPGA Xilinx开发板的Counter程序，计数从0到9999，在板上用4位7段数码管显示，可实现双向计数。-Applicable to FPGA Xilinx development board of the Counter procedures, counting from 0 to 9999, in the board with four 7 digital display, enabling two-way counts.
Update : 2025-02-17 Size : 128kb Publisher : flyingwings
[VHDL-FPGA-Verilog] tlc3548VHDL DL : 0: VHDL实现对TLC3548时序的控制 FPGA控制具有时序简单,速率快等优点-VHDL COUNTER TLC3548
Update : 2025-02-17 Size : 613kb Publisher : 赵惠军
[VHDL-FPGA-Verilog] tlc5628VHDL DL : 1: VHDL实现对TLC5628 AD芯片的时序控制,vhdl对时序的控制不仅高速,而且控制时序清晰,容易实现-vhdl counter tlc5628
Update : 2025-02-17 Size : 353kb Publisher : 赵惠军
[VHDL-FPGA-Verilog] counter DL : 0: 用VHDL语言编写COUNTER-FPGA VHDL COUNTER
Update : 2025-02-17 Size : 111kb Publisher : CG
[VHDL-FPGA-Verilog] counter DL : 0: 基于FPGA平台的，计数器的简单实现过程(Code based on FPGA, a realization of VHDL/counter)
Update : 2025-02-17 Size : 24kb Publisher : yida008

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