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[VHDL-FPGA-Verilog] anjian

Description: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Platform: | Size: 2048 | Author: 汪汪 | Hits:

[VHDL-FPGA-Verilog] primetime

Description: 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
Platform: | Size: 52224 | Author: 张国梁 | Hits:

[VHDL-FPGA-Verilog] yiwei

Description: 跑马灯-是移位寄存器 有6个灯，无延时entity-Bomadeng-shift register is a six lights, without delay entity
Platform: | Size: 1024 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] DELAY1

Description: 本程序以ISE为开发平台，采用VHDL为开发语言，实现了对一个时钟信号延时的功能-the procedures to ISE for the development platform for the development of VHDL language, Implementation of a clock signal delay function
Platform: | Size: 1325056 | Author: 刘小军 | Hits:

[DSP program] ADC_DAC

Description: This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
Platform: | Size: 23552 | Author: gaofeng | Hits:

[Software Engineering] VHDLDelay

Description: 开发环境是FPGA开发工具，描述的是VHDL延时程序，文章中也有程序-Development environment is the FPGA development tools, is described in VHDL delay procedures, the article also have procedures
Platform: | Size: 129024 | Author: horse | Hits:

[VHDL-FPGA-Verilog] FPGAdesignXilinx

Description: 华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。-Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.
Platform: | Size: 1705984 | Author: 高超 | Hits:

[VHDL-FPGA-Verilog] diantikongzhiqi

Description: 本设计是本人的课程设计，基于VHDL的电梯控制器的设计，能够实现12层电梯控制，上下开关，关门延时，提前关门，状态显示，通过波形仿真进行观看结果-The design is my curriculum design, VHDL-based elevator controller design, can achieve 12-storey elevator control, up and down switch, closing delay, early closing, the status display, through to watch the results of waveform simulation
Platform: | Size: 68608 | Author: polly | Hits:

[Communication-Mobile] Mean_64

Description: 原创代码，采用VHDL实现的64点均值滤波。实验测试过，效果良好。可轻松修改成任意点数均值滤波。采用了多点滑动运算，减小了输出延时，最大为3个时钟延迟。可用于AD采样后的滤波处理。-Original code, the use of VHDL to achieve the 64 point mean filter. Experiment tested the results were very good. Can be easily modified into arbitrary point mean filter. Use of multi-point sliding computation, reduces the output delay, a maximum of three clock delay. AD sampling can be used to deal with post-filtering.
Platform: | Size: 2048 | Author: M | Hits:

[VHDL-FPGA-Verilog] fft_statemachine

Description: FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower
Platform: | Size: 7168 | Author: xiaoyuer | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[VHDL-FPGA-Verilog] delay

Description: 用vhdl的状态机实现精确的1us的延时程序-VHDL state machine used to achieve precise 1us delay procedures
Platform: | Size: 1024 | Author: yim | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Documents] IIRfilterFPGA

Description: 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules of the design method and device using VHDL and FPGA implementation of IIR digital filter.
Platform: | Size: 661504 | Author: 杨培科 | Hits:

[VHDL-FPGA-Verilog] QuartusIIandModelSim

Description: 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform.
Platform: | Size: 277504 | Author: 朱雯 | Hits:

[Software Engineering] VHDL

Description: 在电子技术中，频率是最基本的参数之一，又与许多电参量的测量方案、测量结果都有十分密切的关系，因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速，以及便于实现测量过程自动化等优点，是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计，并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门，通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率，最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求，而且具有了单片机的稳定性和成熟性，且控制能力强，是一种低成本，高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Platform: | Size: 220160 | Author: 张林锋 | Hits:

[Compress-Decompress algrithms] delay

Description: 一个可编程延时，只要输入你想的延时周期就可以延时几个周期-a program delay verilog
Platform: | Size: 17408 | Author: liaolain | Hits:

[VHDL-FPGA-Verilog] vhdl-pdelay

Description: programmable delay register (16-bit) in VHDL source code
Platform: | Size: 82944 | Author: bfuclin | Hits:

[VHDL-FPGA-Verilog] delay

Description: 短小易用的时序延迟程序，适用于Xilinx公司的FPGA产品-delay.vhd for Xilinx FPGA
Platform: | Size: 1024 | Author: xhnhd | Hits:

[VHDL-FPGA-Verilog] vhdl-delay

Description: vhdl延时程序,源程序，已调试，可以用-VHDL delay program
Platform: | Size: 1024 | Author: 任贤齐 | Hits:
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