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[ELanguage] lc2

Description: this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: | Size: 43004 | Author: ngzhongsyen | Hits:

[ELanguage] lc2

Description: this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: | Size: 43008 | Author: ngzhongsyen | Hits:

[VHDL-FPGA-Verilog] alarm

Description: 1．6个数码管动态扫描显示驱动 2．按键模式选择(时\分\秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求有闹钟定闹功能，时、分定闹即可，无需时、分、秒定闹。要求使用实验箱左下角的6个动态数码管(DS6 A~DS1A)显示时、分、秒；要求模式按键和调整按键信号都取自经过防抖处理后的按键跳线插孔。-1.6 Digital control of dynamic scanning display driver 2. Mode selection button (when minutes and seconds) and adjust the control 3. Using hardware description language (or a combination of schematic diagram) design, minute and second counter module, key control state machine module, dynamic scanning display driver module, the top-level module. Required to make the alarm set function, the sub-set can make without hour, minute, second set downtown. Require the use of lower-left corner of the experimental box 6 dynamic digital tube (DS6 A ~ DS1A) shows hours, minutes, seconds request mode button and adjust the signal from the button after button after the Anti-shake deal with jack jumper.
Platform: | Size: 621568 | Author: xulina | Hits:

[Wavelet] singt

Description: 实现了方波、正弦波、三角波的输出，同时在LCD模块中用状态机的方法实现LCD的对应显示：当输出正弦波，LCD显示“SIN”；当输出方波，LCD显示“REC”；当输出三角波，显示“TRI”；复位和其它位置波形显示“UNI”。-Realize a square wave, sine wave, triangle wave output, while in the LCD module using the state machine approach to achieve the corresponding LCD display: When the output sine wave, LCD display
Platform: | Size: 1062912 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] LCD

Description: 有限状态机的设计——LCD显示控制实验，用VHDL编写程序，整片报告-Finite state machine design- LCD display control experiments, using VHDL programming, the whole report
Platform: | Size: 147456 | Author: alan | Hits:

[Other] washing

Description: VHDL实现洗衣机控制器程序，功能描述：1. 洗衣机的工作步骤为洗衣、漂洗和脱水三个过程，工作时间分别为：洗衣20 秒，漂洗30 秒，脱水15 秒；可以单独选择其中某一项功能；2. 用显示器件显示洗衣机的工作状态，并倒计时显示每个状态的工作时间， 全部过程结束后，应提示使用者；3. 洗衣过程可以暂停，重新启动后恢复原状态；4、 可以预约洗衣时间。-VHDL controller to achieve washing procedure, function description: 1. The work steps for laundry washing, rinsing and dehydration three processes, working hours are: laundry 20 seconds, rinse for 30 seconds, dehydrated for 15 seconds can individually choose a particular function 2. using display devices display the working status of washing machine, and the countdown show the working hours of each state, all the process is finished, should prompt the user 3. laundry process can pause, restart after the restoration of the original state 4, can appointment laundry.
Platform: | Size: 61440 | Author: 雨姿 | Hits:

[VHDL-FPGA-Verilog] display_fsm

Description: 采用状态机移位显示字符的VHDL代码，包括QUARTUS2的完整工程。-Shifting display with state machine . VHDL code , including the complete QUARTUS2 project.
Platform: | Size: 328704 | Author: simulin_2008 | Hits:

[VHDL-FPGA-Verilog] zidongshouhuojisheji

Description: 本文采用Verilog HDL描述语言实现自动售货机系统的销售动作，用有限状态机进行系统状态描述，自动售货机通电复位时，自动进入系统初始状态，本文设计的自动售货机控制系统主要可以实现投币处理、计算投币总额、输出商品，输出找零、余额计算并显示等功能。-This verilog hdl describe language used for automatic machines system of action, with a limited system of state, state, the vending machine is the power of the system resets when the initial condition, the design of the vending machine control system can be achieved mainly into the slot, the total output of products, output, change and balance computing and display the functions.
Platform: | Size: 34816 | Author: 高菲悦 | Hits:

[VHDL-FPGA-Verilog] LCD_SCREEN

Description: 利用了状态机的53种状态太分别描述LCD显示频的初始化、显示字符串“OK!”的时序图中的详细过程-Use of 53 states of state machine LCD display is too describe the frequency initialized, the string " OK!" The timing diagram of the detailed process
Platform: | Size: 2048 | Author: wulei | Hits:

[VHDL-FPGA-Verilog] button-controled-state-machine

Description: VHDL编的按键去抖，可以实现对目前的显示取反，即1、0、1、0 变换。-VHDL code of the key to shaking, can negate the current display, ie 1,0,1,0 transformation.
Platform: | Size: 228352 | Author: lucy | Hits:

[VHDL-FPGA-Verilog] FPGA_ps2_lcd

Description: FPGA实现 LCD1602 显示 PS/2 键盘的键值,熟悉并掌握液晶 1602 显示屏的使用方法及PS/2键盘的接口标准，学习利用Verilog-HDL语言编写有限状态机实现较为复杂的设计与应用。-LCD1602 FPGA realizing that the PS/2 keyboard keys, familiar with and master the use of liquid crystal display 1602 method and PS/2 keyboard interface standards, study using Verilog-HDL language writing finite state machine achieve comparatively complicated design and application.
Platform: | Size: 81920 | Author: liu | Hits:

[VHDL-FPGA-Verilog] TrafficLightControler

Description: 采用状态机方法设计的交通灯控制器，添加了紧急状态，并且具有时间倒计时显示功能，VHDL源代码-a traffic light controller designed by State machine , a state of emergency is added, and a time countdown display, VHDL source code
Platform: | Size: 1024 | Author: | Hits:

[Windows Develop] fVerrilog_Devr

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL source code quite popular, she will Verilog source together with contribution to everyone: eight priority encoder, multipliers, multiplexers binary switch the BBCD code, adder, subtracter, simple straightforward state machine, four comparators, 7-segment LED, i2c bus, lcd LCD LCD display, DIP switch, serial port, buzzer, matrix keyboard, Marquee, traffic lights, digital clock can be used directly.
Platform: | Size: 3170304 | Author: qtzx | Hits:

[VHDL-FPGA-Verilog] state

Description: 简单状态机数码管显示,Quartus II VHDL设计语言-Asimple state machine digital tube display, Quartus II VHDL design language
Platform: | Size: 1024 | Author: Any | Hits:

[Other] kebenchengxu

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, synchronous counter, sequence detector design. Sequence signal generator, general state machine etc..)
Platform: | Size: 40960 | Author: girl_lily | Hits:

[VHDL-FPGA-Verilog] 1

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc..)
Platform: | Size: 453632 | Author: zidting | Hits:

[VHDL-FPGA-Verilog] 2

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 line -3 line priority encoder, 8 select 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital clock, sequence detector design, general state machine and so on.)
Platform: | Size: 454656 | Author: zidting | Hits:

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