Search - vhdl error correction and detection

Search - vhdl error correction and detection - List

[Develop Tools] rommatlab DL : 0: 错误检测与纠正电路的设计与实现用VHDL语言在CPLD上实现串行通信.doc-error detection and correction circuit design and implementation using VHDL on the CPLD serial communications. D oc
Date : 2008-10-13 Size : 208.63kb User : 1
[Books] rommatlab DL : 0: 错误检测与纠正电路的设计与实现用VHDL语言在CPLD上实现串行通信.doc-error detection and correction circuit design and implementation using VHDL on the CPLD serial communications. D oc
Date : 2025-07-04 Size : 208kb User : 1
[source in ebook] HammingDecoder DL : 0: -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN --- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN
Date : 2025-07-04 Size : 4kb User : djs
[Communication-Mobile] hamming_decoder DL : 0: VHDL编写的Hamming码的程序，可以正确解码--- This Hamming decoder accepts an 8-bit Hamming code and performs single error correction and double error detection.
Date : 2025-07-04 Size : 1kb User : 郑全
[VHDL-FPGA-Verilog] CRCDecoding DL : 0: CRC检错程序。只能检错不能纠错。（40,32）的分组码检错，反馈函数：x8+x7+x4+x3+x+1-CRC error detection process. Not only error detection correction. (40,32) and block code error detection, feedback function: x8+ x7+ x4+ x3+ x+1
Date : 2025-07-04 Size : 144kb User : 李雪茹
[VHDL-FPGA-Verilog] bch-coding DL : 0: In this project, we are implementing the error detection and correction using BCH code (Bose Chaudhuri Hocquenghem). Using VHDL and targeted on FPGA for synthesis of the code. The encoder and decoder combine called as a codec.
Date : 2025-07-04 Size : 5.88mb User : venkata vijay