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[Communication] 用VHDL语言在CPLD_FPGA上实现浮点运算

Description: 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD / FPGA achieve floating-point computation methods
Platform: | Size: 83648 | Author: wei | Hits:

[Program doc] 用VHDL语言在CPLD_FPGA上实现浮点运算

Description: 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD/FPGA achieve floating-point computation methods
Platform: | Size: 82944 | Author: wei | Hits:

[VHDL-FPGA-Verilog] TI6713DSKVHDL

Description: TI6713浮点DSP的DSK的VHDL。比较全面。可以编译运行。-TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
Platform: | Size: 31744 | Author: 丁德锋 | Hits:

[VHDL-FPGA-Verilog] cf_fp_mul

Description: 浮点型的乘法器,采用VHDL语言描述浮点型的乘法器,文中包含测试文件-Floating-point type multiplier using VHDL language to describe the type floating-point multiplier, the text included in the test document
Platform: | Size: 687104 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。-Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.
Platform: | Size: 16384 | Author: WeimuMa | Hits:

[MPI] floatmul

Description: 采用VERILOG 语言进行设计 实现32位浮点数乘法运算 结果已经验证过 放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Platform: | Size: 1024 | Author: NOVEI | Hits:

[VHDL-FPGA-Verilog] Float

Description: 用VHDL语言在CPLD／FPGA上实现浮点运算，资源多多共享,不亦乐乎!-VHDL language used in the CPLD/FPGA to achieve floating-point operations, resources, a lot of sharing, joy!
Platform: | Size: 145408 | Author: wangzhe | Hits:

[VHDL-FPGA-Verilog] multiply

Description: 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
Platform: | Size: 1024 | Author: gulu | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDl在FPGA上实现浮点运算，给初学者使用-VHDL in FPGA to achieve floating-point operations for beginners
Platform: | Size: 145408 | Author: 司马大方 | Hits:

[VHDL-FPGA-Verilog] mul(FLP)

Description: 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
Platform: | Size: 2048 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] div(FLP)

Description: 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除-Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Platform: | Size: 18432 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] floating-point-adder1

Description: 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
Platform: | Size: 9216 | Author: Rosen | Hits:

[VHDL-FPGA-Verilog] gaojindukuaisuchufa

Description: 高精度的浮点数除法运算，基于浮点运算的FPGA实现，单精度浮点数-High-precision floating-point division operation, the FPGA based on the realization of floating-point operations, single precision floating point
Platform: | Size: 81920 | Author: jiachen | Hits:

[VHDL-FPGA-Verilog] FPGArealiztionofdigitalsignalprocessing

Description: 数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHDL代码的程序 cic.exe ---CIC滤波器计算参数的程序 -Digital Signal Processing FPGA realization of practical procedures and documents, there are sine.exe--- input width. Sine wave output of the corresponding csd.exe--- Table mif file to find the integer and fractional number of the volume of standard symbols (canonical signed digit, CSD) Expression Programming fpinv.exe--- countdown procedures for calculation of floating-point form dagen.exe--- documents distributed algorithm to generate HDL " onclick =" tagshow (event) " class =" t_tag " > VHDL program code cic.exe--- CIC filter process parameters
Platform: | Size: 260096 | Author: kevin | Hits:

[Other] f

Description: This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.-This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.
Platform: | Size: 73728 | Author: k | Hits:

[VHDL-FPGA-Verilog] vhdl

Description:
Platform: | Size: 207872 | Author: gjp_rain | Hits:

[VHDL-FPGA-Verilog] floating_multi

Description: Floating point multiplier
Platform: | Size: 1781760 | Author: Alam | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] vhdl-floating-pt

Description: code for fixed & floating point-code for fixed & floating point........
Platform: | Size: 19456 | Author: nagesh | Hits:
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