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最完整最实用的8051的软核,用VHDL语言编写全部原代码,并有详细的注释介绍,对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced multi-purpose microcontroller core or RSIC microcontroller and microprocessor applications SOC very valuable reference
Update : 2008-10-13 Size : 208.51kb Publisher : czy

DL : 0
MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core此公司提供的8051 core很容易在FPGA 上用同时也是学习VHDL的一份不错的进阶实例-MC8051 IP CoreOregano Systems 8-bit Microcontroller IP-Core company for the 8051 core very easy to use in FPGA VHDL is also studying a good example of the SSP
Update : 2025-02-17 Size : 544kb Publisher : 寇锐

增强型8051的VHDL源代码,两个周期执行一条指令,仿真工具为Modelsim,开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
Update : 2025-02-17 Size : 1.91mb Publisher : 柳如飞

最完整最实用的8051的软核,用VHDL语言编写全部原代码,并有详细的注释介绍,对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced multi-purpose microcontroller core or RSIC microcontroller and microprocessor applications SOC very valuable reference
Update : 2025-02-17 Size : 208kb Publisher : czy

8051硬核源码(VHDL),具有全部VHDL代码、测试环境以及说明文档、综合脚本等完整的开发、验证环境,源代码通过ASIC投片,并得到不断完善-8,051 hard-core source code (VHDL), with all VHDL code, testing and documentation, environment, Comprehensive integrity of the script, such as development, certification, the source code for ASIC through films, and has been continually improved
Update : 2025-02-17 Size : 518kb Publisher : 钟方

8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
Update : 2025-02-17 Size : 208kb Publisher : efly

DL : 0
是用VHDL编写的51源代码,对于用FPGA的电子开发单片机人员有很好的参考作用.-VHDL is used to prepare the 51 source code, for the use of single-chip FPGA electronic development staff have a good reference.
Update : 2025-02-17 Size : 95kb Publisher : changdexiao


Update : 2025-02-17 Size : 96kb Publisher : 周华茂

8051的VerilogSourceCode 用于FPGA的NOISii系统-8051 VerilogSourceCode system for FPGA-NOISii
Update : 2025-02-17 Size : 247kb Publisher : 孙建军

8051核Verilog实现源代码,有兴趣的可以看看。-8051 nuclear realize Verilog source code, are interested can look at.
Update : 2025-02-17 Size : 247kb Publisher : 偶的

8051的vhdl源代码,主要针对初学者-8051 VHDL source code, mainly for beginners
Update : 2025-02-17 Size : 9.72mb Publisher : jerry

CPLD/FPGA 入门文档。国内某知名fpga开发商编写的基础教程,共18篇。从使用fpga如何点亮led灯到VGA到8051内核使用方法。如果您是打算学习cpld/fpga,建议先阅读这些文章再选择采购开发板。-CPLD/FPGA entry documents. FPGA developers a well-known domestic basis for the preparation of curricula, a total of 18. From how to use the FPGA to the VGA lit lamp led to the 8051 core to use. If you intend to study cpld/fpga, we suggest that you first read the article and then select the procurement development board.
Update : 2025-02-17 Size : 5.25mb Publisher : gao

这是一个基于xilinx平台的8051处理器文件,用VHDL代码编写-This is a platform based on Xilinx 8051 processor document, using VHDL coding
Update : 2025-02-17 Size : 4.31mb Publisher : 王龙

The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.-The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.
Update : 2025-02-17 Size : 1.36mb Publisher : Francis Wu

alter公司的mcu核,8051ip核,为quartus2设计,其他应该兼容 -alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
Update : 2025-02-17 Size : 8.75mb Publisher : cvdsf

曾经的硕士论文,基于FPGA的8051的soc核研究,用FPGA实现的51核,对FPGA的学习很有帮助-Have master' s thesis, based on the FPGA of the soc of the 8051 nuclear research, with FPGA to achieve the 51 nuclear, helpful for learning FPGA
Update : 2025-02-17 Size : 4.95mb Publisher : 菠萝

vhdl code for 8051 microcontroller
Update : 2025-02-17 Size : 20kb Publisher : Muftah

利用FPGA实现51IP核的下载和运行,并在下载到FPGA后,在改51IP核上运行自己编写的单片机程序,软核51单片机有利的解决了,硬件51单片机的很多限制,提高了单片机的性能。-FPGA realization of the use of nuclear 51IP download and run, and downloaded to the FPGA after the nuclear 51IP to run their own procedures for the preparation of the single-chip, single-chip soft-core 51 favorable resolved, single-chip hardware of many restrictions 51 to improve the performance of a single chip.
Update : 2025-02-17 Size : 1.68mb Publisher : 贾衡天

This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system. -This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system.
Update : 2025-02-17 Size : 4kb Publisher : alex

VHDL/VERILOG FOR 8051 Core
Update : 2025-02-17 Size : 6.68mb Publisher : mss
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