Search - vhdl hdlc

Search - vhdl hdlc - List

[Books] VHDLCIC DL : 0: 台湾国家晶元设计中心VHDL内部培训资料（CIC)-crystal yuan of Taiwan Design Center VHDL internal training materials (CIC)
Update : 2025-02-17 Size : 2.88mb Publisher : 20032211
[ARM-PowerPC-ColdFire-MIPS] hdlc.tar DL : 0: HDLC接口的实现，用VHDL写的，带有文档！-HDLC interface, written using VHDL, with documentation!
Update : 2025-02-17 Size : 173kb Publisher : 刘志刚
[VHDL-FPGA-Verilog] hdlc DL : 0: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Update : 2025-02-17 Size : 3kb Publisher : ditto
[Communication] CRC16_D8.v DL : 0: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试-Ccitt crc checksum completed. HDLC protocol controller for the preparation of the CRC checksum module. Through the simulation test
Update : 2025-02-17 Size : 1kb Publisher :
[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v DL : 0: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Update : 2025-02-17 Size : 1kb Publisher : 张纪强
[VHDL-FPGA-Verilog] hdlc_vhdl DL : 0: This a VHDL implementation of an HDLC controller
Update : 2025-02-17 Size : 176kb Publisher :
[Embeded-SCM Develop] HDLC DL : 1: 在通讯领域中使用相当广泛的HDLC，这是一个参考设计，希望对一些人有用。-In the area of communications used in a wide range of HDLC, which is a reference design with the hope of useful for some people.
Update : 2025-02-17 Size : 2.15mb Publisher : jasonchen
[Embeded-SCM Develop] HDLC DL : 0: hdlc帧接收器包含文件：设计代码测试代码综合脚步说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
Update : 2025-02-17 Size : 437kb Publisher : wangjie
[Other] hdlc_latest.tar DL : 0: HDLC在通讯设备中占有重要地位，本文件提供了完整正确的HDLC的硬件逻辑设计！对设计和学习都具有参考价值-HDLC in the communications equipment plays an important role, this document is to provide a complete hardware HDLC correct logic design! Design and learning have a reference value
Update : 2025-02-17 Size : 173kb Publisher : 欧阳秋
[Embeded-SCM Develop] hdlc-code DL : 0: 用硬件描述语言实现HDLC通道的功能,取代HDLC专用芯片-Hardware description language used to achieve the functions of HDLC channel to replace the HDLC ASIC
Update : 2025-02-17 Size : 11kb Publisher : zhanghf
[Embeded-SCM Develop] hdlc DL : 0: hdlc 总线的vhdl 的样例代码。包含代码和说明文档。-hdlc-bus vhdl sample code. Contains code and documentation.
Update : 2025-02-17 Size : 201kb Publisher : rensijun
[Com Port] insert_zero DL : 0: 可以实现HDLC帧结构中的添零功能，使得信息部分不会和HDLC帧头部分混淆。-can insert zero to the hdlc frame,
Update : 2025-02-17 Size : 1kb Publisher : 王瑜
[VHDL-FPGA-Verilog] trunk-hdlc DL : 0: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Update : 2025-02-17 Size : 184kb Publisher :
[VHDL-FPGA-Verilog] hdlc DL : 0: 基于FPGA的HDLC协议控制器，能完成插零，删除0操作。-HDLC controller base on FPGA
Update : 2025-02-17 Size : 193kb Publisher :
[VHDL-FPGA-Verilog] hdlc DL : 0: HDLC接口协议的FPGA实现使用verilog-design of HDLC
Update : 2025-02-17 Size : 3.53mb Publisher : hanjinchao
[VHDL-FPGA-Verilog] hdlc DL : 0: HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
Update : 2025-02-17 Size : 10kb Publisher : wei
[Com Port] HDLC_VHDL DL : 0: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
Update : 2025-02-17 Size : 11kb Publisher : 卓福洲
[VHDL-FPGA-Verilog] FPGA-HDLC-design DL : 0: 基于FPGA的HDLC协议控制器的设计。FPGA-based HDLC protocol controller design. Pdf-FPGA-based HDLC protocol controller design. Pdf
Update : 2025-02-17 Size : 1.52mb Publisher : iriu
[VHDL-FPGA-Verilog] hdlc_rs DL : 0: 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual process
Update : 2025-02-17 Size : 6kb Publisher : 周宽裕
[VHDL-FPGA-Verilog] HDLC DL : 0: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Update : 2025-02-17 Size : 68kb Publisher : 王强

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