Search - vhdl hdlc code

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[VHDL-FPGA-Verilog] hdlc DL : 0: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Update : 2025-02-17 Size : 3kb Publisher : ditto
[Embeded-SCM Develop] HDLC DL : 0: hdlc帧接收器包含文件：设计代码测试代码综合脚步说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
Update : 2025-02-17 Size : 437kb Publisher : wangjie
[Embeded-SCM Develop] hdlc-code DL : 0: 用硬件描述语言实现HDLC通道的功能,取代HDLC专用芯片-Hardware description language used to achieve the functions of HDLC channel to replace the HDLC ASIC
Update : 2025-02-17 Size : 11kb Publisher : zhanghf
[Embeded-SCM Develop] hdlc DL : 0: hdlc 总线的vhdl 的样例代码。包含代码和说明文档。-hdlc-bus vhdl sample code. Contains code and documentation.
Update : 2025-02-17 Size : 201kb Publisher : rensijun
[VHDL-FPGA-Verilog] hdlc DL : 0: HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
Update : 2025-02-17 Size : 10kb Publisher : wei
[Com Port] HDLC_VHDL DL : 0: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
Update : 2025-02-17 Size : 11kb Publisher : 卓福洲
[VHDL-FPGA-Verilog] core DL : 0: HDLC core, standalone controller with buffers. vhdl source code
Update : 2025-02-17 Size : 17kb Publisher : Hellen
[VHDL-FPGA-Verilog] hdlc DL : 0: HDLC code in vhdl working code
Update : 2025-02-17 Size : 39kb Publisher : hr
[VHDL-FPGA-Verilog] hdlc DL : 0: 这是VHDL语言编写的实现 HDLC通信协议的源代码-This is the HDLC communications protocol source code written in VHDL language
Update : 2025-02-17 Size : 10kb Publisher : sean