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[MPIaltera_avalon_i2c_slave_new

Description: i2c从设备的源码,VHDL语言写的,有疑问请eMail:feng_er_cn@163.com-i2c-source from the equipment, VHDL language, and have questions, please eMail: feng_er_cn@163.com
Platform: | Size: 17408 | Author: 宋大业 | Hits:

[VHDL-FPGA-Verilogi2c_S

Description: I2C Slave module The module contains N accessable Registers when in read Process, all Registers are read at a time when in write Process, only the addressed register are Writeable.
Platform: | Size: 2048 | Author: 李全 | Hits:

[VHDL-FPGA-Verilogi2c_slave

Description: I2c中通信的从机发送和接收信息的Verilog程序测试模块,用Modelsim仿真通过-I2C communication from machine to send and receive information Verilog module test procedures, using ModelSim simulation through
Platform: | Size: 5120 | Author: Tomersun | Hits:

[VHDL-FPGA-Verilogi2c_Sample

Description: verilog在cpld上实现i2c主从设备通讯功能-Verilog CPLD achieved in i2c master-slave communication equipment
Platform: | Size: 718848 | Author: nedazq | Hits:

[Communication-Mobileiic_vhdl

Description: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist -IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
Platform: | Size: 889856 | Author: benny | Hits:

[VHDL-FPGA-Verilogi2c_slave-0.4_VHDL

Description: I2C slave可以作動,請使用 如果有問題請再讓我知道,Thank you -I2C slave can be used for moving, use if there are problems please let me know, Thank you
Platform: | Size: 848896 | Author: mika | Hits:

[Embeded-SCM Developi2c

Description: 来自opencore网站的I2C总线模块,经过验证可以使用-Opencore site from the I2C bus module, you can use a proven
Platform: | Size: 1355776 | Author: 伍波 | Hits:

[VHDL-FPGA-Verilogi2c_slave

Description: i2c slave 分享給大家驗證有點issue-i2c slave to everyone to share a bit authentication issue
Platform: | Size: 362496 | Author: alex | Hits:

[ARM-PowerPC-ColdFire-MIPSI2C

Description: IIC控制器的verilog实现,通过mcu接口对iic slave器件进行控制-IIC controller Verilog realize
Platform: | Size: 348160 | Author: yu | Hits:

[VHDL-FPGA-VerilogI2Cslave1

Description: I2C slave for FPGA and CPLD.
Platform: | Size: 1024 | Author: DAVI | Hits:

[CommunicationI2C_Par_Slave

Description: I2C to 8-bit Parallel Bus Slave Design
Platform: | Size: 3072 | Author: Victor | Hits:

[VHDL-FPGA-VerilogI2C_receiver

Description: 自己写的一个i2c slave的模块,verilog,已经通过验证,可以写可以读,希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
Platform: | Size: 2048 | Author: lj | Hits:

[VHDL-FPGA-Verilogi2c_master_slave_core

Description: I2C master/slave IP core
Platform: | Size: 2180096 | Author: zhanglh | Hits:

[VHDL-FPGA-VerilogVHDL_i2cs_CPLD

Description: 占用寄存器超少的,I2C从模式的代码的VHDL源代码,很有用哦!-Occupation register ultra-small, I2C slave mode code VHDL source code, useful Oh!
Platform: | Size: 20480 | Author: zyxml | Hits:

[OtherI2C_SLAVE

Description: I2C slave端。可支持1带多。本人已经过调试,确认是可用的。-I2C slave side. Can support more than one band. I have been debugging, sure there is available.
Platform: | Size: 1024 | Author: 洛空奇 | Hits:

[Otheri2c_slave

Description: I2C 从设备通讯程序,用于I2C 硬件设计-I2C slave communication program, used to for I2C HW design
Platform: | Size: 3072 | Author: Watt Song | Hits:

[VHDL-FPGA-VerilogI2C

Description: iic verilog 从机程序 包含iic Verilog的主模块,控制模块和io寄存器模块-iic Verilog slave
Platform: | Size: 350208 | Author: ppddxxx | Hits:

[Other Embeded programI2Cslave

Description: i2c slave for i2c control slave block-i2c slave
Platform: | Size: 3072 | Author: wanttofuk | Hits:

[Software Engineeringi2c_master_slave_core_latest.tar

Description: i2c master slave vhdl code
Platform: | Size: 4562944 | Author: abul | Hits:

[VHDL-FPGA-VerilogI2C-Master-_-Slave-Core

Description: 用verilog 实现的 iic 总线编程,包括master,和slave的编程,很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
Platform: | Size: 2181120 | Author: 郭天然 | Hits:
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