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Description: --功能描述
--1 刷卡后产生与本人身份唯一对应的串行二进制码元序列，作为模拟系统的输入信号（此处不妨设为8位学生学号）。
--2 经过串并转换，序列变成一个8位二进制数。
--3 遍历预先存储在rom中的学号信息，逐一和这个8位数相比较，如果有相匹配的信息，显示欢迎字样（此处用一个高电平表示），同时打开栅栏门（也用一个高电平表示）。
-- Functional Description- 1 credit card and identity generated only the corresponding element of the serial binary code sequence, as a simulation system of the input signal (in this case may be set to No. 8 students).- 2 after a string and conversion into a sequence of 8-bit binary number.- 3 pre-stored in the rom traversal of the Student ID information, one by one and compared to the 8-digit, if there is match the message that welcomes the word (here, said with a high), at the same time open the gate ( also expressed a high level).
Platform: |
Size: 1024 |
Author: leizi |
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Description: 利用CASE语句的3-8译码器,3个为数据输入,3个为控制端,分别为S1,S2,S3,输出数据为八位-Use CASE statement 3-8 decoder, three for data entry, three for the control side, namely S1, S2, S3, output data for eight
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Size: 131072 |
Author: sunrier |
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Description: mux 4x1 with 2 control inputs, written in VHDL using 3 mathods: Logic gates, if, case.
the fastest model is the one implemented with the case code.
Platform: |
Size: 1024 |
Author: avi |
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Description: module song(clk,key,song_out,led)
input [7:0] key
input clk
output song_out
output [7:0] led
reg song_reg
reg [21:0] count
reg [19:0] delay
reg [7:0] key_reg
always @(posedge clk)
begin
count=count+1
if((count==delay)&(!(delay==20 d65535)))
begin
count=22 d0
song_reg=!song_reg
end
end
always @(key)
begin
key_reg=key
case(key_reg)
8 b0000_0001: delay=20 d47774 //zhong yin 1 523.3HZ
8 b0000_0010: delay=20 d42568 //zhong yin 2 587.3HZ
8 b0000_0100: delay=20 d37919 //zhong yin 3 659.3HZ
8 b0000_1000: delay=20 d35791 //zhong yin 4 698.5HZ
8 b0001_0000: delay=20 d31888 //zhong yin 5 784HZ
8 b0010_0000: delay=20 d28409 //zhong yin 6 880HZ
8 b0100_0000: delay=20 d25309 //zhong yin 7 987.8HZ
8 b1000_0000: delay=20 d23889 //gao yin 1 1046.5HZ
default: delay=20 d65535
endcase
end
assign song_out=song_reg
文件: song.rar
大小: 357KB
下载: 下载
assign led=key_reg
endmodule
-module song (clk, key, song_out, led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0 ] delay reg [7:0] key_reg always @ (posedge clk) begin count = count+1 if ((count == delay )& (!( delay == 20' d65535))) begin count = 22 ' d0 song_reg =! song_reg end end always @ (key) begin key_reg = key case (key_reg) 8' b0000_0001: delay = 20' d47774 // zhong yin 1 523.3HZ 8' b0000_0010: delay = 20' d42568 // zhong yin 2 587.3HZ 8' b0000_0100: delay = 20' d37919 // zhong yin 3 659.3HZ 8' b0000_1000: delay = 20' d35791 // zhong yin 4 698.5HZ 8' b0001_0000: delay = 20' d31888 // zhong yin 5 784HZ 8' b0010_0000: delay = 20' d28409 // zhong yin 6 880HZ 8' b0100_0000: delay = 20' d25309 // zhong yin 7 987.8HZ 8' b1000_0000: delay = 20' d23889 // gao yin 1 1046.5HZ default: delay = 20' d65535 endcase end assign song_out = song_reg file: song.rar Size: 357KB Download: Download
Platform: |
Size: 365568 |
Author: 罗仲景 |
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