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[Program doc] VHDL 编程要注意问题 DL : 0: VHDL 共定义了 5 种类型的端口，分别是 In, Out,Inout, Buffer及 Linkage，实际设计时只会用到前四种。。。
Date : 2011-07-14 Size : 42.5kb User : z343468478@qq.com
[SCM] Design_and_simulation_of_inout_ports_in_ASIC_desig DL : 0: 在ASIC设计中常常会用到双向IO口来节省系统的硬件资源。但很少有书籍对INOUT口的程序设计和仿真进行介绍，同时，一些书籍介绍的方法在实际中无法使用，本文通过一个图象传感器的事例来详细说明INOUT口的设计方法，并提出一些与实际情况相符的仿真方法-In ASIC design often used in bi-directional IO port to save the system s hardware resources. However, very few books on INOUT mouth design and simulation procedure is introduced, at the same time, a number of books to introduce the method in practice can not be used, the paper through an example of image sensor to a detailed description of the design method INOUT mouth and put forward some actual position in the simulation method
Date : 2025-07-13 Size : 346kb User : sheng
[Embeded-SCM Develop] Inpout32 DL : 0: 32 bit inout mux for embedded design
Date : 2025-07-13 Size : 19kb User : kingtut
[VHDL-FPGA-Verilog] lab4 DL : 0: vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL charout : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL write, read : INOUT STD_LOGIC SIGNAL sdatain_out : OUT STD_LOGIC SIGNAL sdataout_out : OUT STD_LOGIC SIGNAL reset_out : OUT STD_LOGIC SIGNAL sample_clock_out : OUT STD_LOGIC ) END uart -vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL charout : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL write, read : INOUT STD_LOGIC SIGNAL sdatain_out : OUT STD_LOGIC SIGNAL sdataout_out : OUT STD_LOGIC SIGNAL reset_out : OUT STD_LOGIC SIGNAL sample_clock_out : OUT STD_LOGIC ) END uart
Date : 2025-07-13 Size : 10kb User : work
[VHDL-FPGA-Verilog] DMA DL : 0: DMA controller VHDL code entity dma is generic ( ADDR_WIDTH : integer := 16 -- default value DATA_WIDTH : integer := 16 -- default value ) port ( RESET_L : in std_logic CLK : in std_logic DRQ_L : in std_logic DMAACK_L : in std_logic RDY_L : in std_logic DACK_L : out std_logic DMARQ_L : out std_logic WR_L : inout std_logic ADDR : inout std_logic_vector(ADDR_WIDTH - 1 downto 0) DATA : inout std_logic_vector(DATA_WIDTH - 1 downto 0) ) end dma -DMA controller VHDL code entity dma is generic ( ADDR_WIDTH : integer := 16 -- default value DATA_WIDTH : integer := 16 -- default value ) port ( RESET_L : in std_logic CLK : in std_logic DRQ_L : in std_logic DMAACK_L : in std_logic RDY_L : in std_logic DACK_L : out std_logic DMARQ_L : out std_logic WR_L : inout std_logic ADDR : inout std_logic_vector(ADDR_WIDTH - 1 downto 0) DATA : inout std_logic_vector(DATA_WIDTH - 1 downto 0) ) end dma
Date : 2025-07-13 Size : 2kb User : Vlad
[VHDL-FPGA-Verilog] inout-vhdl DL : 0: c p u 读inout 端口的vhdl 程序-Read inout port vhdl program
Date : 2025-07-13 Size : 1kb User : 可新迪
[VHDL-FPGA-Verilog] INOUT DL : 0: 一个实现特定功能的FPGA程序，使用VHDL语言编写，用于排除FPGA影响，检测电路中其他芯片是否正常工作-A function of the FPGA to achieve a specific program, the use of VHDL language for FPGA exclude the impact of other chip detection circuit is working properly
Date : 2025-07-13 Size : 251kb User : 周周
[Education soft system] ReadWrite-RAM-VHDL-source-code DL : 0: This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic
Date : 2025-07-13 Size : 1kb User : ss