Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl interpolation

Search list

[SCM] cic1s2

Description: 单级CIC2倍内插滤波器，用verilogHDL实现-CIC2 times the single-stage interpolation filter, used to achieve verilogHDL
Platform: | Size: 498688 | Author: Carl | Hits:

[matlab] interpolator

Description: 插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现-Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of
Platform: | Size: 966656 | Author: 蔡友 | Hits:

[GDI-Bitmap] Interpolation

Description: 线性插值算法,对高速二次线性插值算法的讨 论-Linear interpolation algorithm, the second high-speed linear interpolation algorithm discussion
Platform: | Size: 125952 | Author: jack | Hits:

[Graph program] ddachabu

Description: 数控里的数字积分，微分插补。 DDA插补-NC integral to the figures, differential interpolation. DDA interpolation
Platform: | Size: 396288 | Author: wengxinpo | Hits:

[VHDL-FPGA-Verilog] hbf

Description: 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
Platform: | Size: 18432 | Author: pll | Hits:

[Windows Develop] vhdl

Description: 在Quarues7.2下实现数字信号的正交相干检波的Bessel内插法-Quarues7.2 achieved in the digital signal of the quadrature coherent detection Bessel interpolation
Platform: | Size: 139264 | Author: zhuwenhua | Hits:

[VHDL-FPGA-Verilog] baseband_verilog

Description: verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器-verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
Platform: | Size: 26624 | Author: 刘新 | Hits:

[Special Effects] h264_intp

Description: 图形图像H264插值算法，应用于图像视频处理-H264 graphic image interpolation algorithm is applied to image video processing
Platform: | Size: 5120 | Author: 朱红梅 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
Platform: | Size: 4096 | Author: 张霄 | Hits:

[VHDL-FPGA-Verilog] myinterpolation

Description: 复杂的插值函数，用于颜色空间转换 verilog-The complex interpolation function for color space conversion verilog
Platform: | Size: 1024 | Author: zhangxinggang | Hits:

[VHDL-FPGA-Verilog] 12345

Description: 本程序为直线插补程序,运用在数控机床上.RAR-This procedure is linear interpolation procedure, used in CNC machine tools. RAR
Platform: | Size: 368640 | Author: 孤帆依梦 | Hits:

[Video Capture] CCD

Description: 本设计主要用来进行图像采集处理，通过摄像头采集图像信息，经过插值算法后存储到外部SDRAM，然后读取图像数据，进行边缘滤波处理后经VGA输出到屏幕上。-This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and then read the image data processed by the edge filter VGA output to the screen.
Platform: | Size: 12288 | Author: 申永帅 | Hits:

[VHDL-FPGA-Verilog] zx

Description: CCD图像的颜色插值算法研究及其FPGA实现 ，这是一篇论文，里面详细介绍了如何实现图像处理的方法-CCD color image interpolation algorithm and its FPGA implementation, which is a paper, which details how to implement image processing method
Platform: | Size: 4647936 | Author: 文 | Hits:

[VHDL-FPGA-Verilog] DDA_xy

Description: 运用Verilog 语言进行数字积分法，将X轴和Y轴进行插补运算。-Verilog language using digital integration method, the X axis and Y axis interpolation operations.
Platform: | Size: 1218560 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] mc

Description: 通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
Platform: | Size: 414720 | Author: 吴汶泰 | Hits:

[VHDL-FPGA-Verilog] DDA

Description: 是用 vhdl 来实现数控中的数字积分法插补-Vhdl to the NC is the number of points in the interpolation method
Platform: | Size: 663552 | Author: 田浩 | Hits:

[VHDL-FPGA-Verilog] LIU

Description: dda 插补法中 由vhdl 语言来实现-dda interpolation achieved by the vhdl language
Platform: | Size: 1187840 | Author: 田浩 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: cic 滤波器，vhdl代码 ，内插与抽取-cic filter ，vhdl code about decination and interpolation
Platform: | Size: 13312 | Author: 唐文明 | Hits:

[VHDL-FPGA-Verilog] filter_lpm_shaping

Description: 4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
Platform: | Size: 16975872 | Author: chen | Hits:

[VHDL-FPGA-Verilog] CPLD-CHABU

Description: 基于cpld 平台，VHDL语言编写，四轴两插补控制程序。包括单轴运动、两轴插补程序、CPLD与ARM通信程序。经过工程实践应用。-Based on the CPLD platform, VHDL language, four two axis interpolation control program. Including the single axis motion, two axis interpolation procedures, CPLD and ARM communication program. Through the engineering practice.
Platform: | Size: 422912 | Author: panshenghu | Hits:
« 12 »

CodeBus www.codebus.net