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[Other resource] IP core

Description: VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
Platform: | Size: 414992 | Author: 周贤 | Hits:

[SourceCode] turbo码 IP core

Description: turbo码 IP core, VHDL编写，Altera公司的，用于信道编码中turbo码的译码
Platform: | Size: 155967 | Author: zhhzhhj@163.com | Hits:

[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 425984 | Author: ken | Hits:

[VHDL-FPGA-Verilog] IP core

Description: VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
Platform: | Size: 414720 | Author: 周贤 | Hits:

[VHDL-FPGA-Verilog] FFT变换的IP核的源代码 VHDL~

Description: FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
Platform: | Size: 31744 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[Other] mp3_decoder

Description: mp3的VHDL实现，包括HUFFMAN编码器，量化器，子带滤波器．可用来开发：ＦＰＧＡ，ＡＳＩＣ．-mp3 of VHDL, including HUFFMAN encoder, quantizer, subband filters. Can be used to develop : FPGA, ASIC.
Platform: | Size: 36864 | Author: 六六 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: | Size: 207872 | Author: 上面的 | Hits:

[ARM-PowerPC-ColdFire-MIPS] IPCORE

Description: 最简单的八位单片机8051的源代码，支持MCS51的汇编语言，可综合，VHDL语言描述，有测试环境-most simple eight SCM 8051 source code, a compilation support MCS51 language, integrated, VHDL description of a test environment
Platform: | Size: 137216 | Author: 许盛 | Hits:

[SCM] mc8051_ug

Description: MC8051 IP Core Synthesizeable VHDL Microcontroller IP-Core-MC8051 Synthesizeable VHDL IP Core Microc ontroller IP-Core
Platform: | Size: 129024 | Author: 周仕凤 | Hits:

[Windows Develop] 2005122512232492458

Description: 本文件是关于vhdl语言的网上最近的免费ip核文件。-VHDL language on the Internet free ip recent nuclear documents.
Platform: | Size: 356352 | Author: 崔战 | Hits:

[VHDL-FPGA-Verilog] S2P_xapp194

Description: VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source
Platform: | Size: 26624 | Author: 苏翔 | Hits:

[Software Engineering] LPM_ff

Description: VHDL中IP核之参数化触发器中文使用介绍-VHDL IP parameters of the nuclear trigger on the use of Chinese
Platform: | Size: 105472 | Author: 孙彬 | Hits:

[Software Engineering] LPM_sub_add

Description: VHDL中IP核之参数化加减法器中文使用介绍-VHDL IP parameters of the nuclear modified instruments used on the use of Chinese
Platform: | Size: 146432 | Author: 孙彬 | Hits:

[VHDL-FPGA-Verilog] AVR_Core

Description: Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
Platform: | Size: 74752 | Author: Casper | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[Other] ptc

Description: PWM/TIMER/COUNTER VHDL IP core
Platform: | Size: 272384 | Author: hehilon | Hits:

[VHDL-FPGA-Verilog] 15-IP-core

Description: 15个免费的IP核 IP核源代码 -15 IP cores
Platform: | Size: 4579328 | Author: chris | Hits:

[TCP/IP stack] stackfiles

Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
Platform: | Size: 81920 | Author: James | Hits:

[VHDL-FPGA-Verilog] vhdl-MIPS

Description: Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
Platform: | Size: 4330496 | Author: ak | Hits:
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