Welcome![Sign In][Sign Up]
Location:
Search - vhdl jiaotongdeng

Search list

[Other resourcejiaotongdeng

Description: 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
Platform: | Size: 394396 | Author: 田冰 | Hits:

[Other resourcejiaotongdeng

Description: 这是用VHDL语言编译的交通灯程序,十分好用
Platform: | Size: 1229 | Author: 史乐 | Hits:

[Other resourcejiaotongdeng

Description: 交通灯VHDL设计,所有程序和顶层逻辑图都有,编译已通过,管脚分配可按实际分配
Platform: | Size: 234657 | Author: zhang | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码-a VHDL prepared by the CPLD on the analog signal source code
Platform: | Size: 394240 | Author: 田冰 | Hits:

[VHDL-FPGA-Verilogjiaotongdengcodes

Description: 实例制作的一个有关交通灯的VHDL代码,从各模块到顶层文件的代码一一列出,详细周到,附带仿真波形图和芯片管脚锁定的相关内容,绝对物超所值。-produced an example of the traffic light VHDL code, from the module to the top of the document sets out a code on January 1, thoughtful details, fringe simulation waveform map and Chip lock the relevant content absolute value for money.
Platform: | Size: 151552 | Author: 潘世雄 | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 这是用VHDL语言编译的交通灯程序,十分好用-This is compiled using VHDL language traffic lights procedure is very easy to use
Platform: | Size: 1024 | Author: 史乐 | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 交通灯VHDL设计,所有程序和顶层逻辑图都有,编译已通过,管脚分配可按实际分配-VHDL design of traffic lights, all the procedures and have a top-level logic diagram, the compiler has passed, according to the actual distribution of pin allocation
Platform: | Size: 234496 | Author: zhang | Hits:

[Compress-Decompress algrithmsjiaotongdeng

Description: 课程设计《交通灯控制的设计》,不知道会不会太简单了。-Curriculum design
Platform: | Size: 657408 | Author: 张云隆 | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: vhdl的铜须等-VHDL copper have to wait
Platform: | Size: 1394688 | Author: waco | Hits:

[assembly languagejiaotongdeng

Description: 设计一个简单的十字路口交通灯。交通灯分东西和南北两个方向,均通过数码管和指示灯指示当前的状态。设两个方向的流量相当,红灯时间45s,绿灯时间40s,黄灯时间5s。-Design a simple traffic lights at a crossroads. Traffic lights at East-West and North-South in both directions, both through the digital control and the current status indicator instructions. Established a considerable traffic in both directions, the alarm time 45s, green time of 40s, yellow time 5s.
Platform: | Size: 1024 | Author: linyao | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 1). 用红、绿、黄三色发光二极管作信号灯。主干道为东西向,有红、绿、黄三个灯;支干道为南北向,也有红、绿、黄三个灯。红灯亮禁止通行;绿灯亮允许通行;黄灯亮则给行驶中的车辆有时间停靠到禁行线之外。 2).由于主干道车辆较多而支干道车辆较少,所以主干道绿灯时间较长。当主干道允许通行亮绿灯时,支干道亮红灯。而支干道允许通行亮绿灯时,主干道亮红灯,两者交替重复。主干道每次放行50秒,支干道每次放行30秒。 在每次由亮绿灯变成亮红灯的转换过程中间,需要亮5秒的黄灯作为过渡,以使行驶中的车辆有时间停靠到禁行线以外。 3). 能实现正常的、即时显示功能。用DE2上的四个七段数码管作为倒计时显示器。分别显示东西、南北方向的红灯、绿灯、黄灯时间。 4).能实现特殊状态的功能显示。设S为特殊状态的传感器信号,当S=1时,进入特殊状态。当S=0时,退出特殊状态。按S后,能实现特殊状态功能: (1)显示器闪烁; (2)计数器停止计数并保持在原来的数据; (3)东西、南北路口均显示红灯状态; (4)特殊状态结束后,能继续对时间进行计数。 5).能实现总体清零功能。按下R后,系统实现总清零,计数器由初始状态开始计数,对应状态的指示灯亮。 -1). With red, green, yellow three-color light-emitting diodes for lights. For the east-west trunk road, has red, green, yellow three lights support for the north-south trunk road, there are red, green, yellow three lights. Red light curfew green permit passage yellow light is to the moving vehicles have the time of call to cut outside the lane. 2). Because of the trunk road vehicles more vehicles and less trunk extension, so a longer green time of a main road. When the main road access permit a green light when the trunk road red sticks. Permit access roads and support a green light when the trunk road red, the two alternating repetition. Allowed 50 seconds for each trunk, branch trunk release each 30 seconds. At each green light into red by the conversion process between the need for five seconds of yellow light as a transitional measure to enable the moving vehicles have the time of call to ban outside lane. 3). To achieve a normal, real-time display. Using DE2 four seventh
Platform: | Size: 2048 | Author: 靓仔 | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 交通灯控制系统VHDL源码,用VHDL语言、MAXPLUS2环境设计实现-VHDL core
Platform: | Size: 401408 | Author: DAVID | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 用VHDL做的交通灯设计-VHDL to do with the design of the traffic lights
Platform: | Size: 198656 | Author: dengchao | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 简单交通灯的VHDL设计,可根据此设计更为复杂的程序-VHDL design of a simple traffic lights, according to this design is more complex procedures
Platform: | Size: 5120 | Author: 胡习武 | Hits:

[Compress-Decompress algrithmsjiaotongdeng_VHDL

Description: 交通控制灯:4个红色指示灯、4个绿色指示灯和4个黄色指示灯模仿路口的东、西、南、北四个方向的红、绿、黄交通灯。控制这些指示灯,使它们按下列规律亮、灭: ①初始状态为四个方向的红灯全亮,时间1秒。 ②东、西方向绿灯亮,南、北方向红灯亮。东、西方向通车,时间5秒。 ③东、西方向黄灯闪烁,南、北方向红灯亮,时间2秒。 ④东、西方向红灯亮,南、北方向绿灯亮。南、北方向通车,时间5秒。 ⑤东、西方向红灯亮,南、北方向黄灯闪烁,时间2秒。 ⑥返回2,继续运行。 ⑦若发生紧急事件,例如救护车、警车通过时,则按下单脉冲按钮,使得的东、西、南、北四个方向的红灯亮。紧急事件结束后,恢复到原状态继续运行使用。-jiaotongdeng VHDL
Platform: | Size: 135168 | Author: myname | Hits:

[Otherjiaotongdeng

Description: 交通灯控制系统的设计和实验报告 8255、8259、8253芯片交通灯-Traffic light control system design and experimental report 8255,8259,8253 chip traffic lights
Platform: | Size: 9216 | Author: 叶倪 | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 用VHDL做的一个交通灯的实验,这个程序的主要功能是:有8个灯,主路和支路分别增加了转弯的灯;有救护车,当救护车按键为高电平时,产生救护车中断,主路和支路红灯亮。同时数码管在当前计数值和全0之间循环显示;有喇叭voice;-Use VHDL to do a traffic light experiment, the main functions of this program: There are eight lights, the main road and slip roads increased by turning the lights the ambulance, when the ambulance when the key is high, resulting in an ambulance interruption, the main road and slip red light. The same time, digital tube in the current count and the whole cycle of display between 0 a loudspeaker voice
Platform: | Size: 13312 | Author: | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 交通灯1.设计一个十字路口的交通灯控制电路,要求 甲车道和乙车道两条交叉道路上的车辆交替 运行, 每次通行时间都设为25秒; 2.要求黄灯先亮5秒,才能变换运行车道; 3.黄灯亮时,要求每秒钟闪亮一次 。-jiaotongdeng
Platform: | Size: 442368 | Author: syh | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: VHDL--十字路口交通灯设计(一组红黄绿交通灯和倒计时设计)-design of luminaire for transportation
Platform: | Size: 77824 | Author: 雇主 | Hits:

[VHDL-FPGA-Verilogjiaotongdeng

Description: 基于VHDL状态机的交通灯设计(已仿真下载实验板测试)(Traffic light design based on VHDL state machine (simulation download, experimental board test))
Platform: | Size: 74752 | Author: 奋斗小二逼 | Hits:
« 12 3 »

CodeBus www.codebus.net