Search - vhdl lms algorithm

[Other resource] FPGA_LMS

Description: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Platform: | Size: 271104 | Author: 黄鹤 | Hits:

[VHDL-FPGA-Verilog] FPGA_LMS

Description: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Platform: | Size: 270336 | Author: 黄鹤 | Hits:

[Other] zishiyinglvbodebiyesheji

Description: 论文针对数字通信系统中，由于码间串扰(ISI)和信道加性噪声的干扰，导致信号在接收端产生误码，设计了基于LMS算法的自适应均衡器(滤波器)，并通过硬件描述语言VHDL和现场可编程逻辑器件FPGA实现均衡器的硬件实现。是一篇标准的毕业论文,有需要的朋友可以拿来做参考-Thesis for digital communications systems, crosstalk due to inter-symbol (ISI) and additive noise channel interference, leading to signals generated in the receiver error, design algorithm based on LMS adaptive equalizer (filter), and through hardware description languages VHDL and Field Programmable Logic Device FPGA hardware equalizer realize realize. Is a standard thesis, there is a need to make friends can be used as reference
Platform: | Size: 2353152 | Author: YZ | Hits:

[VHDL-FPGA-Verilog] ante

Description: 智能天线自适应LMS算法，假设具有4个天线阵元。-Smart antenna adaptive LMS algorithm, the assumption that with four million antenna array.
Platform: | Size: 4096 | Author: 黄虎 | Hits:

[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar

Description: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Platform: | Size: 14336 | Author: Arun | Hits:

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[Other resource] FPGA_LMS

[VHDL-FPGA-Verilog] FPGA_LMS

[Other] zishiyinglvbodebiyesheji

[VHDL-FPGA-Verilog] ante

[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar

[VHDL-FPGA-Verilog] AdaptiveLMSequalizer

[VHDL-FPGA-Verilog] lms

[VHDL-FPGA-Verilog] fir_lms

[Embeded-SCM Develop] LMS

[VHDL-FPGA-Verilog] ERROR_COUNTING_BLOCK

[VHDL-FPGA-Verilog] WEIGHT_UPDATE_BLOCK

[VHDL-FPGA-Verilog] lmsFPGA

[VHDL-FPGA-Verilog] vhdl_lms

[Other] Quartus-VHDL-lms

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