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[Other resource] SKRETD(low_power)

Description: 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Platform: | Size: 380854 | Author: xialu | Hits:

[Other] PSpice仿真实践

Description: PSpice一本很好的教程。Pspice仿真器是一个全功能的模拟和混合信号仿真器,它支持从高频系统到低功耗IC设计的任何电路。-PSpice a very good tutorial. Pspice simulator is a fully functional analog and mixed-signal simulator, its support from the high-frequency systems to low-power IC design of any circuit.
Platform: | Size: 3291136 | Author: 王真 | Hits:

[Other Embeded program] SKRETD(low_power)

Description: 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Platform: | Size: 380928 | Author: xialu | Hits:

[Program doc] Viterbi

Description: 三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Platform: | Size: 451584 | Author: helei_zju | Hits:

[Other] clock

Description: 本文介绍一种利用 EDA技术 和VHDL 语言 ,在MAX+PLUSⅡ环境下,设计了一种新型的智能密码锁。它体积小、功耗低、价格便宜、安全可靠,维护和升级都十分方便,具有较好的应用前景-This paper presents a use of EDA technologies and VHDL language, in MAX+ PLUS Ⅱ environment, design a new type of intelligent locks. Its small size, low power consumption, cheap, safe, reliable, maintenance and upgrade are very convenient, has good application prospects
Platform: | Size: 67584 | Author: 叶仔 | Hits:

[Other] low_assumption

Description: 低功耗的设计与实现方法！ CMOS电路低功耗设计的基本方法和途径！ -Low-power design and implementation! Low-power CMOS circuit design of the basic ways and means!
Platform: | Size: 122880 | Author: 朱笑愚 | Hits:

[Other] lp_guide3

Description: 集成电路低功耗设计指导手册，内含大量低功耗设计方法。-Integrated circuits low-power design guide, containing a large number of low-power design methodology.
Platform: | Size: 4316160 | Author: zinger liu | Hits:

[VHDL-FPGA-Verilog] Design_of_Traffic_Light_Controller_Based_on_VHDL.r

Description: :传统的交通灯控制器多数由单片机或PLC来实现,文中介绍了基于VHDL硬件描述语言进行交通灯控制 器设计的一般思路和方法。选择XIL INX公司低功耗、低成本、高性能的FPGA芯片,采用ISE5. X和MODELSIM SE 6. 0开发工具进行了程序的编译和功能仿真。最后给出了交通灯控制器的部分VHDL源程序和仿真结果,仿 真结果表明该系统的设计方案正确。-Traffic light controller is usually developed bymicro p rocessor or PLC. This paper introduces the gen2 eral design methods of traffic light controller base on VHDL ( hardware descrip tion language). the FPGA chip of XIL2 INX Corporation was chosen with the low power loss, the low cost and the high performance, the XIL INX ISE5. X andMODELSIM 6. 0 development toolswas used to comp ile and stimulate. Finally, The VHDL source p rogrammer and simulating results of traffic light controller are given. The simulating results show that the design method is cor2 rect
Platform: | Size: 434176 | Author: li | Hits:

[VHDL-FPGA-Verilog] lowpowerfir

Description: This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the system. The power consumption of various arithmetic architectures has been investigated, and the results have been provided in the intial report (FIRLowPowerConsiderations.doc). These results have enabled the correct power/performance optimization for the FIR filter design.
Platform: | Size: 447488 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

Description: ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.
Platform: | Size: 379904 | Author: phitoan | Hits:

[VHDL-FPGA-Verilog] 2

Description: EDA的课程设计，利用VHDL语言、PLD设计基于FPGA的出租车计费系统，选用ALTERA公司低功耗、低成本、高性能的FPGA芯片EPF10K10，以MAX+PLUSⅡ软件作为开发平台，设计了出租车计费器系统程序并进行了编译，功能仿真和下载。使其实现计费以及预置和模拟汽车启动、加速、停止、暂停等功能，并动态扫描显示车费数目。-EDA curriculum design, the use of VHDL language, PLD design FPGA-based taxi billing system, the company selected ALTERA low power, low-cost, high-performance FPGA chip EPF10K10, the MAX+ PLUS Ⅱ software as a development platform, design a taxi billing system and make the compilation process, functional simulation, and download. To achieve automotive billing and pre-and simulation start, accelerate, stop, pause and other functions, and the number of dynamic scans indicate the fare.
Platform: | Size: 8192 | Author: wang | Hits:

[VHDL-FPGA-Verilog] 4_Low_Power_High_Performance_SRAM_Design_Using_VH

Description: Low Power High Performance SRAM Design Using VHDL By Mahendra Kumar, Kailash Chandra
Platform: | Size: 396288 | Author: shankar | Hits:

[VHDL-FPGA-Verilog] hardh264-src.tar

Description: VhDl code for low-power design of h.264 system architecture
Platform: | Size: 36864 | Author: azaam | Hits:

[VHDL-FPGA-Verilog] bb74300fc549

Description: vhdl code low-power design of h.264 system architecture
Platform: | Size: 880640 | Author: azaam | Hits:

[VHDL-FPGA-Verilog] bhaskar

Description: Wireless sensor networks for low power design vhdl
Platform: | Size: 1118208 | Author: Neeraj | Hits:

[Software Engineering] 10509019_final.pdf

Description: design and implementation of faster and low power multipliers in vhdl
Platform: | Size: 883712 | Author: murthy | Hits:

[Industry research] Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas

Description: The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.-The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.
Platform: | Size: 172032 | Author: farbosein | Hits:

[VHDL-FPGA-Verilog] Low-Power-FIR-Filter

Description: FIR滤波在数字信号领域中很大作用。这个源码很大帮助VHDL工程师或学习者。里面包含说明书。-This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.
Platform: | Size: 437248 | Author: 金铁男 | Hits:

[Other] jeas_reversable-vedic-multiplier

Description: reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
Platform: | Size: 557056 | Author: paramu | Hits:

[Report papers] Optimization technology of step motor control system

Description: In this paper, a FPGA-based step motor driver implementing adjustable subdivision and sine pulse width modulation is introduced. This driving system can solve the high subdivision problem, increase the driving torque and angle resolution, and smooth the motor angle. Employing the bottom-top design method, the circuit was described by the VHDL language, synthesized by Xilinx ISE integrated environment, and simulated by Modelsim in both behavior level and gate level through the PLI interface. According to experiment’s result, this driver has the advantages of easy debugging, high anti-interference ability, larger driving power, low volume and low cost in large scale production.
Platform: | Size: 623104 | Author: jionad123 | Hits:

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