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[Other resource] VHDL学习手册

Description: VHDL学习手册-VHDL study manual
Platform: | Size: 5460377 | Author: Paladin | Hits:

[Other resource] 1076 IEEE Standard VHDL Language Reference Manual.

Description: 1076-2002 IEEE Standard VHDL Language Reference Manual-1076-2002 IEEE Standard VHDL Language Ref validated Manual
Platform: | Size: 867086 | Author: 巫涛 | Hits:

[VHDL-FPGA-Verilog] VHDL学习手册

Description: VHDL学习手册-VHDL study manual
Platform: | Size: 5459968 | Author: 站长 | Hits:

[VHDL-FPGA-Verilog] 1076 IEEE Standard VHDL Language Reference Manual.

Description: 1076-2002 IEEE Standard VHDL Language Reference Manual-1076-2002 IEEE Standard VHDL Language Ref validated Manual
Platform: | Size: 867328 | Author: 巫涛 | Hits:

[Other] VhdlLanguageReferenceMmanualIEEE1076

Description: vhdl language reference manual IEEE1076(2004.10)-VHDL language reference manual IEEE1076 (2004.10)
Platform: | Size: 1301504 | Author: 谭贤豪 | Hits:

[Books] VHDLTEACH

Description: VHDL教程 VHDL与数字电路设计 使用手册-VHDL Guide VHDL and digital circuit design manual
Platform: | Size: 4498432 | Author: 20032211 | Hits:

[Software Engineering] FPGA

Description: 系统应用FPGA技术，通过VHDL编程，在CPLD上实现。电子琴的基本原理是产生各个音符对应的频率，将频率放大后驱动喇叭发出音响。该电子琴包括手动弹奏与自动演奏两种功能，其中手动弹奏时还可录音回放。文中叙述了电子琴的设计原理和分块实现的方法，详细介绍各模块的设计及模块之间的连接组合方法，还包括电子琴的使用说明。-System FPGA technology, the adoption of VHDL programming, to achieve in the CPLD. The basic principles of flower is the corresponding frequency of each note will be the frequency of enlarged issued after the driver speaker audio. Playing the organ, including manual and automatic playing two functions, which also play recordable playback manually. The paper describes the design of flower and block the realization of the principle of the method, details of the module design and module combination of the connection between the methods also include the use of electric piano note.
Platform: | Size: 49152 | Author: 严术骞 | Hits:

[VHDL-FPGA-Verilog] VHDLreference

Description: 英文版的VHDL黄金参考手册，文章中解答了很多关于实际设计中遇到的问题-English version of the VHDL Golden Reference Manual, the article answers a lot about the actual design problems encountered
Platform: | Size: 182272 | Author: 周青 | Hits:

[SCM] 356B18accelerator

Description: 356b18加速度计的中文使用手册，事我自己翻译的，要是有不足的地方希望大家见谅。对于安装和使用该传感器有一定的帮助。-356b18 accelerometer Chinese user manual, do my own translation, if there are deficiencies in the hope that we will be forgiven. For installation and use of the sensor is certainly helpful to them.
Platform: | Size: 1310720 | Author: wangscorpio | Hits:

[VHDL-FPGA-Verilog] ALTERA

Description: altera中文的器件选型手册，大家开发fpga采用altera的器件的话可以-altera Chinese manual device selection, the development of U.S. altera FPGA device used, then can
Platform: | Size: 706560 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] Edition

Description: VHDL可重用英文书,书中有许多对VHDL可重用的具体介绍,是一般的相关书籍所没有的.-VHDL reusable English book has a lot of reusable VHDL specific introduction is generally not related books.
Platform: | Size: 4564992 | Author: 徐民 | Hits:

[VHDL-FPGA-Verilog] Music_Player

Description: 用vhdl实现的电子琴中的音乐播放模块，可以实现自动播放以及手动播放功能-Using VHDL realize the electric piano in the music player module, you can realize automatic and manual player playback
Platform: | Size: 2048 | Author: 万玉龙 | Hits:

[VHDL-FPGA-Verilog] 1076IEEEStandardVHDLLanguageReferenceManual

Description: IEEE 1076 Standard VHDL Language Reference Manual
Platform: | Size: 865280 | Author: enhom | Hits:

[Other] John.Wiley.Sons.Smart.Card.Handbook

Description: smart card的经典手册。里面详细介绍了smart card的设计方法，标准及相关的测试等内容。-smart card classic manual. Inside the smart card described in detail the design of methods, standards and related testing and so on.
Platform: | Size: 11005952 | Author: 张泉 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: VHDL学习手册,适合初学VHDL者和在设计VHDL时有疑问者。-VHDL learning manual, suitable for novice VHDL and VHDL in the design of those who have doubt.
Platform: | Size: 2984960 | Author: 黄忻杰 | Hits:

[VHDL-FPGA-Verilog] VHDL-Cookbook

Description: VHDL快速查看 入门手册 还有少量精品例子-VHDL Quick View Getting Started manual was also a small number of fine examples
Platform: | Size: 237568 | Author: Duke | Hits:

[VHDL-FPGA-Verilog] vhdl-2008-just-the-new-stuff-systems-on-silicon.r

Description: VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual—Amendment 1: Procedural Language Application Interface.
Platform: | Size: 800768 | Author: chane | Hits:

[VHDL-FPGA-Verilog] 1076_ieee_standard_vhdl_language_reference_manual.

Description: 1076 ieee standard vhdl language reference manual-1076 ieee standard vhdl language reference manual.pdf
Platform: | Size: 933888 | Author: alomar | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: （1）用VHDL语言编写程序，在EDA实验板上实现 （2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。 （3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。 用VHDL语言编写程序，在EDA实验板上实现 （4） 整点报时。 （5）. 闹钟功能。 （6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Platform: | Size: 4096 | Author: malon | Hits:

[VHDL-FPGA-Verilog] VHDL-Xilinx-ISE-a-ModelSim

Description: VHDL上机手册（基于Xilinx ISE & ModelSim）-VHDL-on manual (based on the Xilinx ISE & ModelSim)
Platform: | Size: 831488 | Author: l | Hits:
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