Search - vhdl modulation

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[VHDL-FPGA-Verilog] MPSK调制与解调VHDL程序与仿真 DL : 0: MPSK调制与解调VHDL程序与仿真,具有很高的参考价值!!vhdl代码!-MPSK modulation and demodulation process and VHDL simulation, high reference value! ! VHDL code!
Update : 2025-02-17 Size : 78kb Publisher : 温暖感
[VHDL-FPGA-Verilog] PL_FSK DL : 0: 数字通信系统通信系统调制解调（PL_FSK）VHDL建模，包括发送和接受模块-Digital Communication System Communication System modulation and demodulation (PL_FSK) VHDL modeling, including sending and receiving modules
Update : 2025-02-17 Size : 183kb Publisher : 万金油
[VHDL-FPGA-Verilog] FSKmodemodulateVHDLprogramme DL : 0: FSK调制与解调的vhdl源代码与仿真指导，是word文档打开。-FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
Update : 2025-02-17 Size : 51kb Publisher : 吴涛
[VHDL-FPGA-Verilog] ASK.VHDL DL : 0: ASK调制VHDL程序及仿真基于VHDL硬件描述语言，对基带信号进行ASK振幅调制-ASK modulation VHDL simulation based on the procedures and VHDL hardware description language, the baseband signal amplitude modulation ASK
Update : 2025-02-17 Size : 41kb Publisher : 少龙
[VHDL-FPGA-Verilog] PSK.VHDL DL : 0: CPSK调制VHDL程序及仿真基于VHDL硬件描述语言，对基带信号进行调制-CPSK modulation VHDL simulation based on the procedures and VHDL hardware description language, the baseband signal modulation
Update : 2025-02-17 Size : 71kb Publisher : 少龙
[source in ebook] some-usful-vhdl-source-code DL : 0: 一些实用的VHDL源码，有各种信号调制的，还有LCD控制的，出租车计价器等等源码。-some practical VHDL source code, a variety of signal modulation, there is the LCD control. taximeters, etc. source.
Update : 2025-02-17 Size : 1.22mb Publisher : 雨风
[Communication] 16QAMModulationVHDL DL : 0: 实现16QAM系统调制仿真，附件里面WORD文档是整合的程序，其他的是源文件-Realize 16QAM modulation system simulation, annex inside the WORD document is an integrated process, the other is the source file
Update : 2025-02-17 Size : 9kb Publisher : 丁巍
[VHDL-FPGA-Verilog] alaw DL : 0: 使用VHDL实现通信脉冲编码调制（PCM）中的a律转换，并实现串并、并串转换。-Use VHDL to achieve communication pulse code modulation (PCM) of a law conversion, and to achieve and string, and string conversion.
Update : 2025-02-17 Size : 5kb Publisher : wl
[VHDL-FPGA-Verilog] PSK_VHDL DL : 0: CPSK调制VHDL程序 --文件名：PL_CPSK --功能：基于VHDL硬件描述语言，对基带信号进行调制 -VHDL procedures CPSK modulation- the file name: PL_CPSK- features: VHDL hardware description language based on the base-band signal modulation
Update : 2025-02-17 Size : 71kb Publisher : huangsong
[ELanguage] QPSKvhdl DL : 0: QPSK的VHDL调制解调 FPGA设计思路思想-QPSK modulation and demodulation of the VHDL design thinking FPGA
Update : 2025-02-17 Size : 1.54mb Publisher : liming
[VHDL-FPGA-Verilog] VHDL DL : 0: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Update : 2025-02-17 Size : 37kb Publisher : 袁玉佳
[VHDL-FPGA-Verilog] pwm__vhdl DL : 0: 一个基于vhdl语言的脉冲宽度调制。并且有两个脉冲输出-Vhdl language-based pulse width modulation. And two pulse output
Update : 2025-02-17 Size : 883kb Publisher : 邹细男
[VHDL-FPGA-Verilog] FSK_PSK_tiaozhidianlusheji DL : 0: FSK/PSK调制电路设计，基于vhdl和quartus2-FSK/PSK modulation circuit design, based on the vhdl and quartus2
Update : 2025-02-17 Size : 27kb Publisher : neversee
[source in ebook] VHDL DL : 0: 16QAM调制器的Verilog HDL程序，可以实现16QAM调制-16QAM modulator Verilog HDL procedures, 16QAM modulation can be achieved
Update : 2025-02-17 Size : 1kb Publisher : 吴丹
[SCM] dds DL : 0: 基于DDS的调频调相通过改变频率控制字来控制程序编译过搭过硬件可以实现-FM Based on DDS phase modulation by changing the frequency control word to control the program compiled the hardware can be achieved take-off
Update : 2025-02-17 Size : 449kb Publisher : 梁梁
[VHDL-FPGA-Verilog] module_dem DL : 1: 用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现-Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation
Update : 2025-02-17 Size : 5.79mb Publisher : yu
[VHDL-FPGA-Verilog] CPFSK DL : 0: CPFSK调制的相关资料文档，有一定的参考意义。-CPFSK modulation information documents, there is a certain reference value.
Update : 2025-02-17 Size : 565kb Publisher : niuniu
[DSP program] fangz DL : 0: 数字通信系统的仿真，包括调制解调，上下变频，加入了高斯白噪声，并且每个步骤都生成相应的图形-Digital communication system simulation, including the modulation and demodulation, the upper and lower frequency, by adding Gaussian white noise, and each step generates the appropriate graphics
Update : 2025-02-17 Size : 34kb Publisher : maominchao
[VHDL-FPGA-Verilog] ASK-VHDL DL : 0: 基于VHDL硬件描述语言，对基带信号进行ASK振幅调制-VHDL hardware description language based on the ASK baseband amplitude modulation signal
Update : 2025-02-17 Size : 41kb Publisher : 海玲
[VHDL-FPGA-Verilog] PSK-VHDL DL : 0: PSK调制与解调VHDL程序及仿真，仿真通过-PSK modulation and demodulation process, and VHDL simulation, simulation by
Update : 2025-02-17 Size : 71kb Publisher : 海玲

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