Search - vhdl ping pong

[VHDL-FPGA-Verilog] 128×16ram

Description: VHDL程序设计的RAM存储器，双端口，128×16比特-VHDL programming RAM memory, dual-port, 128 × 16 bits
Platform: | Size: 1024 | Author: petri | Hits:

[VHDL-FPGA-Verilog] pingpong

Description:
Platform: | Size: 75776 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 实现乒乓缓存，用verilog语言编写！-Realize cache ping-pong, using Verilog language!
Platform: | Size: 165888 | Author: zhl | Hits:

[VHDL-FPGA-Verilog] SRAM-PINGPANG

Description: 超声视频图像需要实时地采集并在处理后在显示器上重建，图像存储器就必须不断地写入数据，同时又要不断地从存储器读出数据送往后端处理和显示[11]。为了满足这种要求，可以在采集系统中设置2片容量一样的SRAM，通过乒乓读写机制来管理。任何时刻，只能有1片SRAM处于写状态，同时也只有1片SRAM处于读状态。工作期间，2片SRAM都处于读写状态轮流转换的过程，转换的过程相同，但是状态错开，从而保证数据能连续地写人和读出祯存.-Real-time ultrasound video images need to collect and deal with the reconstruction after the display, image memory must be continually write data, while at the same time continuously sent from the memory读出数据back-end processing and display [11]. To meet this requirement, you can set up collection system capacity of two different SRAM, read and write through the ping-pong mechanisms to manage. At any time, can only have a SRAM in write state, but also the only one at a time the state of SRAM. Work, two SRAM read and write are in the process of converting a state of rotation, the conversion process of the same, but the state staggered to ensure that data can be continuously written and read out Qizhen depositors.
Platform: | Size: 1024 | Author: smj1980 | Hits:

[source in ebook] VHDL

Description: 高质量的VHDL代码乒乓处理FIFO缓存-High-quality VHDL code deal with ping-pong FIFO cache
Platform: | Size: 1024 | Author: wode | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[VHDL-FPGA-Verilog] pingpangVHDL

Description: 据说是 vhdl的乒乓ram 代码提供给大家做个参考吧 -It is said VHDL code of the ping-pong ram available to the U.S. to be a reference to it
Platform: | Size: 1024 | Author: 白饭 | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 关于乒乓操作的，对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
Platform: | Size: 166912 | Author: 敬亮 | Hits:

[Button control] ppong

Description: FGPA code to implement a ping-pong game. There will be LEDs simulating the path of ball , and two button representing the player. The player should hit the button when the ball reach his end. If the player hit the ball, it will go to the other player. When the player does not hit at the right time, he will lose.-FGPA code to implement a ping-pong game. There will be LEDs simulating the path of ball , and two button representing the player. The player should hit the button when the ball reach his end. If the player hit the ball, it will go to the other player. When the player does not hit at the right time, he will lose.
Platform: | Size: 196608 | Author: lzm | Hits:

[VHDL-FPGA-Verilog] fft_1024_hdl

Description: 一个 1024 点 FFT ，基 4 蝶形运算架构， 5级流水，乒乓内存，有测试环境。-A 1024-point FFT, Radix-4 butterfly structure operation, five water, ping-pong memory, a test environment.
Platform: | Size: 18432 | Author: wei | Hits:

[MPI] dpram2

Description: ram的读写，使用状态机完成，两片ram实现乒乓操作-ram read and write, using the state machine completed, two ping-pong operation to achieve ram
Platform: | Size: 1024 | Author: 李群 | Hits:

[VHDL-FPGA-Verilog] sram_060803

Description: SRAM的读写代码，对SRAM进行了乒乓操作，用VHDL语言进行设计，很有参考价值，甚至可以直接复制代码来进行自己的设计-SRAM read and write code, ping-pong operation carried out on the SRAM, using VHDL language design, of great reference value, or even directly copy the code to carry out their own designs
Platform: | Size: 198656 | Author: hongliang | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 两人乒乓球游戏机是用9个发光二极管代表乒乓球台，用点亮的发光二极管按一定的方向移动来表示球的运动。在游戏机的两侧各设置一个开关，即击球开关Hit A，HitB。甲乙二人按乒乓球比赛规则来操作开关。当甲按动击球开关时，靠近甲的第一个二极管亮，然后发光二极管由甲向乙依次点亮，代表乒乓球的移动。当球过网（中点）时，乙方可以击球。若乙方提前或是没击中球则判乙方失分，甲方的计分牌自动加分。然后重新发球，比赛继续。比赛直到一方分数达到11分时，比赛结束。 -Two table tennis game with nine leds with light table tennis, representing the light emitting diode according to certain direction to move the ball movement. On both sides of the game to set A switch, namely the ball Hit A HitB, switch. 2 party b according to table tennis match rules switch. When a button when hitting switch near the first light emitting diode, then led by a to b, in light of the table tennis movement. Representative When the ball over the net (middle), party b can hit. If party b or didn t hit the ball ahead is sentenced to party b, party a s scoreboards automatic points. Then again, continue to serve. Until one reaches 11 points, the end of the match.
Platform: | Size: 4096 | Author: Shine | Hits:

[VHDL-FPGA-Verilog] VHDL-Ping-pong

Description: 基于VHDL的乒乓球游戏的设计，包含代码，仿真结果等。-Table tennis game in VHDL-based design, including the code, the simulation results.
Platform: | Size: 3072 | Author: 李皓 | Hits:

[VHDL-FPGA-Verilog] pingpangqiu

Description: 使用vhdl语言设计的乒乓球比赛游戏机，一个由甲乙双方参赛，有裁判的三人乒乓球游戏机。用8个发光二极管代表乒乓球台，中间两个发光二极管兼做乒乓球网，两边各代表参赛双方的位置，用点亮二极管按照一定方向移动来表示球的运动。在游戏机的两侧各设置两个开关，一个是发球开关（af，bf），另一个是击球开关（aj，bj）。甲乙二人按乒乓球比赛的规则来操作开关。点亮，代表乒乓球在移动。比赛一直进行到一方几分为11分，该局结束，记分牌清零，可以开始新的一局比赛。 -Using VHDL language design table tennis game consoles, a competition by both parties, the referee of three table tennis game. Double as a table tennis net with eight light-emitting diodes on behalf of a ping-pong table, in the middle of two light-emitting diodes, on both sides of the representatives participating both lit diode according to a certain direction to move to represent the movement of the ball. Setting two switches, each on both sides of the ride is a tee switch (af, bf), another is batting switch (aj, bj). B two table tennis competition rules to operate the switch. On behalf of table tennis in mobile. The game has been carried out to the party a bit for 11 minutes it ends scoreboard is cleared, you can start a new innings.
Platform: | Size: 492544 | Author: 陈小龙 | Hits:

[VHDL-FPGA-Verilog] toplevel_png

Description: top level for ping pong game on vhdl
Platform: | Size: 1024 | Author: Abdul | Hits:

[Other Games] Pingpong

Description: A Altera DE-2 ping pong game which using a PS/2 keyboard to control.VGA port of DE-2 will be the output of the game video.The sources code build from VHDL code on Quartus II.-A Altera DE-2 ping pong game which using a PS/2 keyboard to control.VGA port of DE-2 will be the output of the game video.The sources code build from VHDL code on Quartus II.
Platform: | Size: 18709504 | Author: kkddaa | Hits:

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[VHDL-FPGA-Verilog] 128×16ram

[VHDL-FPGA-Verilog] pingpong

[VHDL-FPGA-Verilog] pingpang

[VHDL-FPGA-Verilog] SRAM-PINGPANG

[source in ebook] VHDL

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] pingpangVHDL

[VHDL-FPGA-Verilog] pingpang

[Button control] ppong

[VHDL-FPGA-Verilog] fft_1024_hdl

[MPI] dpram2

[VHDL-FPGA-Verilog] sram_060803

[VHDL-FPGA-Verilog] pingpang

[VHDL-FPGA-Verilog] VHDL-Ping-pong

[VHDL-FPGA-Verilog] pingpangqiu

[VHDL-FPGA-Verilog] toplevel_png

[Other Games] Pingpong

[Other Games] Pong.tar

[Other Games] Ping-Pong-Game-in-Actel-VHDL

[VHDL-FPGA-Verilog] PPRAM-test

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