Description: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic. Platform: |
Size: 14336 |
Author:Arun |
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Description: 3．完成系统的FPGA程序开发与调试，主要包括FFT，IFFT，CMUL和转置
存储控制等模块，在此基础上，重点介绍了一种基于DDR SDRAM的行写行读高
效转置存储算法，在采用该算法进行转置存储操作时，读写两端的速度相匹配，
满足流水线操作要求，提高了整个系统的实时性。最后介绍了采用CORDIC算法
实现复图像求模运算的方法，分析了算法的硬件实现结构，并给出了基于FPGA
的实现方法及仿真结果。-he FPGA s development and debugging are implemented,including FFT, IFFT, CMUL and C0ntrol of CTM．Based Oll this，Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced．When using CTM with this algorithm，me speed of reading and writing maItches and meets the requirement of pipelined operation．Finally a method of model implementation for complex image based on CORDIC algorithm is introduced．The algorithm’s hardware implementation structure is analysed, and implementation methodology and simulation results are given Platform: |
Size: 5155840 |
Author:mabeibei |
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Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related. Platform: |
Size: 822272 |
Author:wang |
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Search - vhdl pipelined implementation