Search - vhdl stopwatch

[VHDL-FPGA-Verilog] vhdl-多功能电子表

Description: 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Platform: | Size: 5120 | Author: 王继东 | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟有闹钟,秒表,时钟,日期等功能秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] watch

Description: vhdl语言编写的一个秒表源码，包括在LCD上显示的部分，附带TB源码，对初学者比较实用-VHDL language, a stopwatch source, including the LCD display part, incidental TB source, more practical for beginners
Platform: | Size: 98304 | Author: ronniy | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 电子秒表，可以显示0.01S到59’59”99.带有开始、暂停、复位于一键的控制功能。-Electronic stopwatch, can display 0.01S to 59 59 99. With a moratorium, rehabilitation located in a key control functions.
Platform: | Size: 1024 | Author: jacky | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字秒表的设计，reset为归零设置，start为重新计时设置-Design of digital stopwatch, reset to zero settings, start time set for the re-
Platform: | Size: 309248 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Platform: | Size: 577536 | Author: xie | Hits:

[Documents] vhdl

Description: 6位LED电子钟,非常实用实做过实验，自动报时，秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
Platform: | Size: 4096 | Author: 王睿 | Hits:

[VHDL-FPGA-Verilog] VHDL312vh6

Description: 包含若干个VHDL小例子，有交通灯，电子琴，简易秒表，等等，交通灯已经测试过，根据自己的需要，稍微改动，很好用！-VHDL contains a number of small example, there is traffic lights, Electronic organ, simple stopwatch, and so on, traffic lights have been tested, according to their own needs, slightly altered, very good use!
Platform: | Size: 327680 | Author: lee gilbert | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
Platform: | Size: 1647616 | Author: 王蕊 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] StopWatch

Description: Verilog 编写的秒表程序，在数码管上显示，带有清0和暂停键-Stopwatch Implemented by Verilog hdl
Platform: | Size: 584704 | Author: 洪磊 | Hits:

[SCM] watch

Description: VHDL编写的秒表，经过试验了，用的应该还可以-VHDL stopwatch prepared, tested, and can be used
Platform: | Size: 164864 | Author: wangzw | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
Platform: | Size: 266240 | Author: ly | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: （1）用VHDL语言编写程序，在EDA实验板上实现（2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。（3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。用VHDL语言编写程序，在EDA实验板上实现（4）整点报时。（5）. 闹钟功能。（6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Platform: | Size: 4096 | Author: malon | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.
Platform: | Size: 1024 | Author: 王唐小菲 | Hits:

[VHDL-FPGA-Verilog] STOPWATCH

Description: 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to the study, can help you complete VHDL language curriculum design.
Platform: | Size: 661504 | Author: 王亮 | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch-design

Description: 数字秒表的设计报告，用VHDL语言编写程序，实现分析讨论中各种功能，分别进行编译并生成相应的模块，然后将这些模块连接起来形成电路图，并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the corresponding module, and then connect these modules together to form a circuit, and compiled simulation.
Platform: | Size: 375808 | Author: 吴亮 | Hits:

[Software Engineering] VHDL-maobiao

Description: VHDL秒表，运行过，可以用，供初学者学习-VHDL stopwatch running, you can use for beginners to learn
Platform: | Size: 1969152 | Author: xiaxia | Hits:

[VHDL-FPGA-Verilog] VHDL-stopwatch-reports-and-code

Description: 用VHDL实现数字秒表的设计实践，并用FPGA下载进行功能验证！-Using VHDL the digital stopwatch design practice, and functional verification of FPGA download!
Platform: | Size: 1895424 | Author: 一个好人 | Hits:

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[VHDL-FPGA-Verilog] vhdl-多功能电子表

[Documents] VHDL

[Software Engineering] clock

[VHDL-FPGA-Verilog] watch

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] stopwatch

[Documents] vhdl

[VHDL-FPGA-Verilog] VHDL312vh6

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] StopWatch

[SCM] watch

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] stopwatch

[VHDL-FPGA-Verilog] STOPWATCH

[VHDL-FPGA-Verilog] Digital-stopwatch-design

[Software Engineering] VHDL-maobiao

[VHDL-FPGA-Verilog] VHDL-stopwatch-reports-and-code

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