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[VHDL-FPGA-Verilog] MPEG

Description: MPEG-2TS 流嵌入控制数据的设计，设计的要求是用控制数据替换MPEG-2 TS 流中的空帧-MPEG-2TS control data stream embedded in the design, the design requirements is to control data to replace MPEG-2 TS stream of the air frame
Platform: | Size: 251904 | Author: wq | Hits:

[mpeg mp3] auk_ts_input

Description: ts流输入virilog源码-ts stream input source virilog
Platform: | Size: 7168 | Author: zjk_220 | Hits:

[VHDL-FPGA-Verilog] MPEG-2_TS

Description: MPEG2中的TS流！讲解怎么用控制信息代替空包！-MPEG2 in TS stream! Explain how to use control information in place of empty packet!
Platform: | Size: 44032 | Author: dragon | Hits:

[Windows Develop] TS_sychrous_check

Description: 该模块主要用于MEPGII TS流同步检测。当连续检测到3个TS包同步时，输出一个同步有效信号，在该同步信号的驱动下，TS包写入FIFO中。该模块对检测TS包的有无及是否同步特别有效，希望对做数字电视的朋友有所帮助。-The module is mainly used for synchronous detection MEPGII TS stream. When detected in three consecutive TS packets simultaneously, the output of a sync signal, in which the sync signal driven, TS packet writing in FIFO. The module for detection of whether the TS packet and whether synchronization particularly effective, and they hope to make digital television a friend help.
Platform: | Size: 49152 | Author: huangdecheng | Hits:

[mpeg mp3] TS_control

Description: MPEG-2 TS 流嵌入控制数据的设计 TS流中的空帧很多，将某些空帧（188字节）全换为控制数据DIN（即在该空帧位置处构成一新的数据帧），按照TS流格式进行传输。TS流数据帧中的数据和控制数据不能出现丢失。-MPEG-2 TS stream control data embedded in the design of TS stream a lot of empty frames, some empty frame (188 bytes) for the control of the whole data for DIN (that is, in the empty frame position constitute a new data frame), TS stream format in accordance with the transmission. TS stream data frame of data and control data can not be lost.
Platform: | Size: 2048 | Author: zhaochuan | Hits:

[VHDL-FPGA-Verilog] DEMUX

Description: Demultiplexor vhdl code
Platform: | Size: 1024 | Author: Avatar | Hits:

[mpeg mp3] FPGAbasedMPEG2TS

Description: 基于FPGA的MPEG-2TS码流实时分析与检测系统.nh-FPGA-based MPEG-2TS stream real-time analysis and detection system. Nh
Platform: | Size: 3542016 | Author: zly | Hits:

[Other] RS(204.188)design

Description: RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。 仿真波形： rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[VHDL-FPGA-Verilog] RS_ENCODER

Description: DVBC RS编码,标准TS流输入输出接口!-DVBC RS encoder
Platform: | Size: 3072 | Author: sun mingang | Hits:

[Windows Develop] SYMBOL_MAPPING

Description: DVB QAM符号映射!已经应用于产品.标准TS流接口-DVB QAM symbol mapping! Has been applied to products. Standard TS stream interface
Platform: | Size: 2048 | Author: sun | Hits:

[Voice Compress] 238257858255_IO_vhdl

Description: ts input transport stream input
Platform: | Size: 1024 | Author: samet | Hits:

[TCP/IP stack] terabit_ethernet

Description: TERABIT ETHERNET 具体介绍 包括Time-Space Carrier Sense Multiple Access (CSMA/TS)-TERABIT ETHERNET introduction （Time-Space Carrier Sense Multiple Access (CSMA/TS)）
Platform: | Size: 691200 | Author: zhouli | Hits:

[Software Engineering] 040402~~

Description: 虽然与SRAM相比，SDRAM需要额外的控制逻辑，有更复杂的时序要求，需要定时刷新，但是由于SDRAM具有单位空间存储容量大和价钱便宜的优点，因而被许多的嵌入式开发者所青睐。为此，针对这种情况，必须设计SDRAM控制器。为了降低系统成本，本课题采用FPGA技术，并使用VHDL语言研究了FPGA与SDRAM的存储器接口实现问题。-Abstract In order to expand the SDRAM’S storage capacity of the TS一101 processor，a method is pro— posed for implementing the SDRAM controller based on FPGA．The characteristics of the corresponding SDRAM are analyzed and the schematic diagrams and the timing are given．The function of modules and per- formance of SDRAM storage board are described．The design method of modularization is adopted in FPGA． This design expands the SDRAM’S storage capacity of the TS-101 processor to 512Mbytes．
Platform: | Size: 254976 | Author: zhangying | Hits:

[VHDL-FPGA-Verilog] kongbao2

Description: 信道传输中所需的TS码流仿真包，数字电视的类似信号格式，VHDL编写，简单明了，希望对大家有帮助-The desired channel transmission simulation package TS stream, similar signal formats of digital TV, VHDL written, clear and simple, we want to help
Platform: | Size: 1024 | Author: 欧阳凯 | Hits:

[VHDL-FPGA-Verilog] 091220111singalcpu

Description: 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, ts, imm blez rs, imm j target -Verilog HDL language or VHDL language to write the single-cycle CPU design. Able to complete the following 16 designated: add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, ts, imm blez rs, imm j target
Platform: | Size: 9529344 | Author: 徐帆 | Hits:

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