Description: 该代码是用VHDL编写的用以实现5/3无损小波变换。压缩包内附有详细的说明。-the VHDL code is used to prepare for the realization of the 5/3 wavelet transform prejudice. Compression packet containing a detailed explanation. Platform: |
Size: 3304448 |
Author:黄飞 |
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Description: 這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder-This is a two-dimensional lift-style 9/7 discrete wavelet of Verilog source code, this is Encoder Platform: |
Size: 7728128 |
Author:chiahao |
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Description: 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-High-speed image compression encoder the structural design of VLSI Research. Kdh quite the level of doctoral dissertation. Which describes in detail how to design the structure of wavelet transform VLSI. Verilog hdl design and structure of the assessment Platform: |
Size: 1733632 |
Author:黄辉 |
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Description: 53整数小波滤波,编译已经成功,仿真也已经通过,是网上着的资料-53 integer wavelet filter, has been successfully compiled, the simulation has also been adopted, is online with information Platform: |
Size: 1005568 |
Author:teamcen |
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Description: 小波变换的VHDL代码,内带正变换逆变换的测试文件。-Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file. Platform: |
Size: 18432 |
Author:Janee |
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Description: 完成一维小波变换一级分解。此文件包含小波变换的mallat算法,经测试完全正确。-Completed a one-dimensional wavelet transform decomposition. This file contains the mallat wavelet transform algorithm, the test is correct. Platform: |
Size: 1558528 |
Author:羽凡 |
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Description: 此文件配合小波变换mallat算法分解重构使用,能够完成整个设计。-This file with the wavelet transform decomposition and reconstruction algorithm mallat used to complete the entire design. Platform: |
Size: 15399936 |
Author:羽凡 |
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Description: 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述:-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code: Platform: |
Size: 2048 |
Author:张龙升 |
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Description: 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述:-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code: Platform: |
Size: 3072 |
Author:张龙升 |
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