Search - video vhdl

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[VHDL-FPGA-Verilog] gen_itu DL : 0: ITU645视频格式输出,速率可调节.多种格式可调整.-ITU645 video format output, adjustable rate. Adjustable in multiple formats.
Update : 2025-02-17 Size : 5kb Publisher : 王晶
[VHDL-FPGA-Verilog] FPGA-Ethernet-video DL : 0: 介绍如何用FPGA实现网络视频传输的设计论文，很有参考价值。-Introduce how to realize the network video transmission FPGA design papers, a good reference.
Update : 2025-02-17 Size : 186kb Publisher : 曾祥进
[Embeded-SCM Develop] saa7113 DL : 0: saa7113视频解码芯片外围电路设计原理图，可供大家参考设计-saa7113 video decoder chip peripheral circuit design schematics, reference design for everyone
Update : 2025-02-17 Size : 17kb Publisher : 穆垚
[Multimedia program] video_compression_systems.tar DL : 0: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Update : 2025-02-17 Size : 182kb Publisher : 王弋妹
[File Format] FPGA264AVC DL : 0: 在FPGA上实现H_264AVC视频编码标准-In the FPGA to achieve H_264AVC Video Coding Standard
Update : 2025-02-17 Size : 112kb Publisher : 长衫
[VHDL-FPGA-Verilog] video DL : 0: 用VHDL实现视频控制程序，包含详细的实现代码-Using VHDL video control procedures, including the realization of the detailed code
Update : 2025-02-17 Size : 409kb Publisher : 王刚
[Graph program] VGA_TV DL : 0: 一个模拟视频输入转VGA视频输出的Verilog程序-An analog video input to VGA video output of the Verilog program
Update : 2025-02-17 Size : 26kb Publisher : 李华
[VHDL-FPGA-Verilog] scaler DL : 0: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Update : 2025-02-17 Size : 9kb Publisher : wgy
[Multimedia program] nova.tar DL : 0: video decoder full hardware
Update : 2025-02-17 Size : 729kb Publisher : esl
[Special Effects] video_process_base_on_DSPandFPGA DL : 0: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Update : 2025-02-17 Size : 534kb Publisher : John
[SCM] saa7113 DL : 0: 视频解压缩程序（用verilog语言实现）-Video decompression procedures [verilog]
Update : 2025-02-17 Size : 8kb Publisher : xiaoheng
[VHDL-FPGA-Verilog] vga_core(vhdl) DL : 0: vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中-vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
Update : 2025-02-17 Size : 449kb Publisher : 程荣
[Software Engineering] HDTV_Video_Pattern_Generator DL : 0: HDTV Video Pattern Generator 设计参考-HDTV Video Pattern Generator
Update : 2025-02-17 Size : 102kb Publisher : yaodao
[Video Capture] VideoDemystified DL : 0: 视频信号的形成，基本概念，相关标准，格式，以及视频处理的过程-Video Demystified- Handbook for the Digital Engineer (4th Ed) [Elsevier, 2005]
Update : 2025-02-17 Size : 4.39mb Publisher : li nan
[Multimedia program] video DL : 0: 数字视频信号流水线处理的4个实例：实例1：产生蓝屏实例2：产生彩色条测试图像实例3：叠加移动的物体实例4：叠加动态视频-Four examples of digital video pipeline
Update : 2025-02-17 Size : 17kb Publisher : li nan
[Special Effects] VIDEO-FPGA DL : 0: 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
Update : 2025-02-17 Size : 5.75mb Publisher : 王刚
[VHDL-FPGA-Verilog] xapp288 DL : 0: This the reference design file for XAPP288 " SDI Video Decoder" it includes both VHDL and Verilog versions -This is the reference design file for XAPP288 " SDI Video Decoder" it includes both VHDL and Verilog versions
Update : 2025-02-17 Size : 67kb Publisher : zhangxinxin
[Other] video DL : 0: vga controller 設計資料，非常基礎且實用-vga controller design information, and is based on practical
Update : 2025-02-17 Size : 192kb Publisher : 陳彥丞
[VHDL-FPGA-Verilog] xapp460 DL : 2: 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）-Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
Update : 2025-02-17 Size : 1.52mb Publisher : wicky
[VHDL-FPGA-Verilog] ourdev_247126 DL : 0: his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize. Running the Design-his design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize. Running the Design
Update : 2025-02-17 Size : 158kb Publisher : 路啄米

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