Search - viterbi code in verilog

Search - viterbi code in verilog - List

[Other] viterbigen DL : 0: viterbi verilog 代码生成程序，产生多项式可自由指定-viterbi verilog code generation process, resulting in freedom of the specified polynomial
Update : 2025-02-17 Size : 52kb Publisher : ryan zhang
[VHDL-FPGA-Verilog] viterbidecoder DL : 0: viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
Update : 2025-02-17 Size : 5kb Publisher : zhouli
[VHDL-FPGA-Verilog] viterbi DL : 0: This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.-This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
Update : 2025-02-17 Size : 639kb Publisher : Nagendran
[VHDL-FPGA-Verilog] Control DL : 0: 维特比译码器控制器部分Verilog代码-The controller part of the Viterbi decoder in Verilog code
Update : 2025-02-17 Size : 1kb Publisher : 王阳
[VHDL-FPGA-Verilog] viterbideoderupdated DL : 0: Viterbi decoder source code is in verilog with CRCv-Viterbi decoder source code is in verilog with CRCv
Update : 2025-02-17 Size : 2kb Publisher : hr
[Modem program] VITERBI DL : 0: In this case is a viterbi algorithm code for decoding the convolutional code, using verilog HDL language. This code provide the method of deconvolution of the convolutional code
Update : 2025-02-17 Size : 2kb Publisher : kimdaeyoung
[VHDL-FPGA-Verilog] verilog-juanjima DL : 1: 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and its error correction performance is often better than the block code, and (2,1,7) convolutional code has been used in modern satellite communication system. Viterbi decoding algorithm can maximize the performance of convolutional codes. Here is the Verilog HDL design (2,1,7) convolutional code encoder module and decoder module based on Viterbi algorithm, the decoder is designed using the parallel structure and the decoding speed is fast.
Update : 2025-02-17 Size : 10kb Publisher : 邓博于、