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[Windows Develop] ViterbiFPGA DL : 0: Date : 2025-07-13 Size : 3.61mb User : 鲁东旭
[Other Embeded program] SKRETD(low_power) DL : 0: 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Date : 2025-07-13 Size : 372kb User : xialu
[Communication-Mobile] viterbi213 DL : 0: Date : 2025-07-13 Size : 3.19mb User : 潘应云
[Program doc] Viterbi DL : 0: 三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Date : 2025-07-13 Size : 441kb User : helei_zju
[VHDL-FPGA-Verilog] viterbi DL : 0: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Date : 2025-07-13 Size : 61kb User : yaoyongshi
[Program doc] viterbi DL : 0: 基于XilinxFPGA的高速Viterbi回溯译码器-Based on retrospective XilinxFPGA high-speed Viterbi decoder
Date : 2025-07-13 Size : 194kb User : mediative
[Program doc] viterbi DL : 0: 维特比译码器的asic设计的相关论文-Viterbi Decoder asic design related articles
Date : 2025-07-13 Size : 271kb User : mediative
[VHDL-FPGA-Verilog] Viterbi_IP DL : 0: viterbi译码器的IP核，可以直接编译使用-viterbi decoder IP core, the compiler can directly use
Date : 2025-07-13 Size : 74kb User : nianln
[VHDL-FPGA-Verilog] husw DL : 0: 用VHDL语言设计维特比解码器是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Date : 2025-07-13 Size : 1kb User : hsw0320
[VHDL-FPGA-Verilog] Viterbi DL : 0: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Date : 2025-07-13 Size : 8kb User : 蔡敏
[Communication-Mobile] urn_nbn_se_liu_diva-6949-1__fulltext DL : 0: Viterbi decoder algorithm
Date : 2025-07-13 Size : 549kb User : Hossam Ahmed
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Date : 2025-07-13 Size : 3kb User : xiongherui
[VHDL-FPGA-Verilog] Viterbi_decoder DL : 0: Viterbi译码器的编解码器的设计用Verilog实现-Viterbi decoder。Verilog
Date : 2025-07-13 Size : 63kb User : 李风飞
[Software Engineering] vit_dec DL : 0: viterbi decoder implementation
Date : 2025-07-13 Size : 5kb User : rocky mehta
[VHDL-FPGA-Verilog] viterbi DL : 0: viterbi decoder with convolutional encoder
Date : 2025-07-13 Size : 1.33mb User : phani
[VHDL-FPGA-Verilog] reinformationregardingapplicationfee DL : 0: paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format -paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
Date : 2025-07-13 Size : 421kb User : awa
[VHDL-FPGA-Verilog] viterbi_binary_hard_c DL : 0: vhdl code for viterbi decoder
Date : 2025-07-13 Size : 4kb User : anjali
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog code for viterbi encoder and decoder
Date : 2025-07-13 Size : 13kb User : kamran
[VHDL-FPGA-Verilog] viterbi.decoder DL : 0: Date : 2025-07-13 Size : 11kb User : thang
[VHDL-FPGA-Verilog] VD-vhdl-Code DL : 0: this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
Date : 2025-07-13 Size : 7kb User : shishir

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