Search - viterbi decoder vhdl code

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[Windows Develop] ViterbiFPGA DL : 0: 论文格式，内含Viterbi编解码器的完整vhdl代码，文件为.nh格式-paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
Date : 2008-10-13 Size : 3.61mb User : 鲁东旭
[ELanguage] turbo_VHDL DL : 1: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M yHDL cycle / bit accurate model * Synthesizable VHDL model
Date : 2008-10-13 Size : 151.14kb User : 鲁京
[Other] viterbi213 DL : 0: 提供了一个硬判决的viterbi译码器（2，1，3）有源程序及算法描述，未成定稿，只供参考（vhdl 语言描述） -provided a hard decision of the Viterbi Decoder (2,1, 3) the source code and the algorithm description, from his position as final, for reference (vhdl Description Language)
Date : 2008-10-13 Size : 3.19mb User : 潘应云
[Windows Develop] ViterbiFPGA DL : 0: Date : 2025-07-06 Size : 3.61mb User : 鲁东旭
[Communication-Mobile] turbo_VHDL DL : 0: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Date : 2025-07-06 Size : 151kb User :
[Communication-Mobile] viterbi213 DL : 0: Date : 2025-07-06 Size : 3.19mb User : 潘应云
[VHDL-FPGA-Verilog] husw DL : 0: 用VHDL语言设计维特比解码器是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Date : 2025-07-06 Size : 1kb User : hsw0320
[VHDL-FPGA-Verilog] Viterbi DL : 0: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Date : 2025-07-06 Size : 8kb User : 蔡敏
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Date : 2025-07-06 Size : 3kb User : xiongherui
[VHDL-FPGA-Verilog] viterbi_for_bch DL : 0: Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
Date : 2025-07-06 Size : 1kb User : shahifaqeer
[Software Engineering] fwdrsapapers DL : 0: Fpga Based Enviuronemen paper format that includes Viterbi Decoder complete VHDL code for the document . Nh format -Fpga Based Enviuronemen paper format that includes Viterbi Decoder complete VHDL code for the document paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
Date : 2025-07-06 Size : 1.06mb User : awa
[VHDL-FPGA-Verilog] reinformationregardingapplicationfee DL : 0: paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format -paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format
Date : 2025-07-06 Size : 421kb User : awa
[VHDL-FPGA-Verilog] viterbi_binary_hard_c DL : 0: vhdl code for viterbi decoder
Date : 2025-07-06 Size : 4kb User : anjali
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog code for viterbi encoder and decoder
Date : 2025-07-06 Size : 13kb User : kamran
[Other] viterbi213 DL : 0: 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
Date : 2025-07-06 Size : 2.54mb User : jenny
[VHDL-FPGA-Verilog] VD-vhdl-Code DL : 0: this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
Date : 2025-07-06 Size : 7kb User : shishir
[VHDL-FPGA-Verilog] The-viterbi-algorithm-(1) DL : 0: Vetrbi decoder VHDL code
Date : 2025-07-06 Size : 381kb User : rajaisking
[Other] viterbi_1 DL : 0: low power convolution encoder and Viterbi decoder using vhdl code
Date : 2025-07-06 Size : 180kb User : Abhi
[3G develop] turbocodes_latest.tar DL : 0: 基于sova算法的Turbo码解码VHDL工程文件，非常经典，包含Python高层仿真代码。-Turbo Decoder Release 0.3 MAIN FEATURES - * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model AUTHOR David Brochart <dbrochart@opencores.org>
Date : 2025-07-06 Size : 165kb User : John Smith