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[
VHDL-FPGA-Verilog
]
viterbidecoder
Description:
viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
Platform:
|
Size:
5120
|
Author:
zhouli
|
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Search - viterbidecoder in verilog
Search - viterbidecoder in verilog