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Description: 目 錄 1
目 錄
Unix基本指令 第一章
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1.1 本章教學大綱...................................................1-2
1.2 Unix的歷史......................................................1-2
1.3 Unix基本指令簡介..........................................1-5
1.4 編輯器vi.........................................................1-45
1.5 Unix的基本檔案系統.....................................1-51
1.6 相關網站.........................................................1-60
1.7 課後習題相關網站.........................................1-61
CMOS VLSI設計概念與Design Flow 第二章
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2.1 本章教學大綱...................................................2-2
2.2 IC的各種設計方法..........................................2-2
2.3 MOS電晶體....................................................2-10
2.4 CMOS的技術.................................................2-16
2.5 Bottom Up與Top Down設計........................2-25
2.6 Full Custom IC的設計流程............................2-29
2.7 Design Frame work II之檔案結構..................2-33
2.8 CAD/CAE軟體的資料格式標準....................2-40
2.9 國科會晶片實現中心 ( CIC )........................2-42
2.10 作業.................................................................2-44
2 目 錄
第
如何進入Cadence 三章
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3.1 如何進入Cadence.............................................3-2
3.2 如何將Cadence 4.3.X的Lib轉成OPUS-97A 4.4版的Lib......................................................3-4
3.3 建立新的Library............................................3-12
3.4 建立新的cellview...........................................3-17
Schematic 第四章
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4.1 Schematic 指令介紹.......................................4-2
4.2 Schematic繪圖視窗選項介紹..........................4-3
4.3 實作範例：建立一Buffer的Schematic View4-27
4.4 將Schematic View轉出網路檔 (netlist) 的CDL out...................................................................4-30
Symbol 第五章
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5.1 Symbol View快速選擇介紹.............................5-2
5.2 Symbol繪圖視窗選擇項介紹...........................5-4
5.3 實作範例：建立一Buffer的Symbol View...5-22
Layout 第六章
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6.1 Layout View......................................................6-2
6.2 Layer Selection Window (LSW) 視窗..............6-3
6.3 Layout快速選項列介紹...................................6-3
6.4 Layout View繪圖視窗選擇項介紹..................6-6
6.5 實作範例：建立一Buffer的Layout View....6-37
目 錄 3
第
Dracula 七章
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7.1 Dracula介紹.....................................................7-2
7.2 DRC(Design Rule Checking).............................7-2
7.3 DRC錯誤範例說明........................................7-15
7.4 DRC Error Message.........................................7-24
7.5 ERC錯誤範例說明.........................................7-27
7.6 LVS(Layout vs. Schematic Check)..................7-32
7.7 LVS錯誤範例說明.........................................7-49
7.8 LVS的錯誤型態.............................................7-62
7.9 LPE(Layout Parameter Extraction)..................7-78
I/O Circuit及Package 第八章
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8.1 I/O Circuit概述.................................................8-2
8.2 基本分類...........................................................8-4
8.3 CIC之I/O PAD................................................8-9
8.4 I/O PAD的規劃..............................................8-28
8.5 範 例.............................................................8-34
8.6 包裝 (Package)...............................................8-36
SPICE Simulation 第九章
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9.1 本章教學大綱...................................................9-2
9.2 SPICE Simulation的基本概念..........................9-2
9.3 SPICE的語法...................................................9-5
9.4 用HSPICE來模擬............................................9-8
9.5 用PSPICE來模擬..........................................9-53
9.6 用IsSPICE來模擬..........................................9-58
9.7 用SBTSPICE來模擬.....................................9-68
4 目 錄
第
Design Guide 十章
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10.1 本章教學大綱.................................................10-2
10.2 Design for Reliability......................................10-2
10.3 Design for Testability....................................10-27
範例：JK FF 第十一章
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11.1 本章教學大綱.................................................11-2
11.2 JK正反器電路圖............................................11-2
11.3 建立所有的邏輯閘.........................................11-3
11.4 JK正反器之schematic及symbol view........11-10
11.5 用HSPICE來模擬JK正反器之狀態輸出...11-11
11.6 Debug............................................................11-16
11.7 PDRACULA的驗證.....................................11-29
教育性晶片製作申請程序及範例 附錄一
Design Rules實例 (Mead & Conway) 附錄二
XV使用說明 附錄三
將電路加入IOPAD的方法 附錄四
加入IOPAD的幾個動作 附錄五
積體電路電路布局保護法 附錄六
參考資料
Platform: |
Size: 9318659 |
Author: g9676612@cycu.edu.tw |
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Description: EDA Tools for Layout auto place & route Taiwan, NSYSU EE VLSI Lab, PDF file Total 43 pages
Platform: |
Size: 850319 |
Author: packet110 |
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Description: 超大规模集成电路设计中，布图规划的布局表示B*-tree和相应算法的实现，在linux环境中编译运行-VLSI design, floorplanning express the layout and the corresponding B*- tree algorithm, in the linux environment running the compiler
Platform: |
Size: 221184 |
Author: 陈望川 |
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Description: 这是布局布图领域具有里程碑意义的一篇文章,这篇文章的出现大大推动了VLSI研究领域前进的步伐-This is the layout of the layout of a milestone in the field of an article, which greatly promoted the emergence of VLSI research advance
Platform: |
Size: 120832 |
Author: wufeng |
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Description: The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:
* Custom IC layout
* Schematic Capture (digital and analog)
* Textual Languages such as VHDL and Verilog
-The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:* Custom IC layout* Schematic Capture (digital and analog)* Textual Languages such as VHDL and Verilog
Platform: |
Size: 15382528 |
Author: 杨晓斐 |
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Description: The sequence-pair was proposed to represent a rectangle
packing and a placement, and is used to place modules automatically
in VLSI layout design. Several decoding methods
of sequence-pair were proposed. However, encoding methods
are not found except the original one called “gridding”.
Platform: |
Size: 101376 |
Author: aditi2000 |
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Description: BOI version of Steiner tree construction, practical and popular for manhattan VLSI routing, generate a Steiner minimum tree for given set of terminals in a layout plane-BOI version of Steiner tree construction, practical and popular for manhattan VLSI routing, generate a Steiner minimum tree for given set of terminals in a layout plane
Platform: |
Size: 365568 |
Author: Ernesto Liu |
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Description: Construct buffered routing tree for VLSI interconnects in a Manhanttan layout plane for a given set of terminals, guarantee polarity of the terminals agree with each other
Platform: |
Size: 33792 |
Author: Ernesto Liu |
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Description: FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs-FengShui: custom ASIC layout placement for gigascale VLSI circuits, for gate array, sea of gate and standard cell designs, scales well into million gate designs
Platform: |
Size: 584704 |
Author: Ernesto Liu |
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Description: Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization.
Platform: |
Size: 15185920 |
Author: 朋友 |
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Description: 在管理科学、计算机科学、分子物理学、生物学、超大规模集成电路设计、代码设计、图像处理和电子工程等领域中，存在着大量的组合优化问题。例如，货郎担问题、最大截问题、0—1背包问题、图着色问题、设备布局问题以及布线问题等，这些问题至今仍未找到多项式时间算法。-In management science, computer science, molecular physics, biology, VLSI design, code design, image processing and electronic engineering and other fields, there are a large number of combinatorial optimization problems. For example, the traveling salesman problem, the maximum cut problem ,0-1 knapsack problem, graph coloring problems, equipment problems and wiring layout problems, these problems have yet to find a polynomial time algorithm.
Platform: |
Size: 185344 |
Author: 张浩 |
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Description: 主要内容：
• 版图设计概念；
• CMOS VLSI制造工艺；
• Tanner版图流程举例（反相器）。-Main content: • layout design concepts • CMOS VLSI manufacturing process • Tanner map of the process instance (inverter).
Platform: |
Size: 579584 |
Author: kro |
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Description: Oracle 云计算战略
• 提供私有云和公有云两种解决方案供客户选择
• 提供全面、集成的 SaaS、PaaS 和 IaaS 产品
• 让客户根据业务需要采用云
最小面积的矩形。由于各种包装
是不可数无穷的，成功优化的关键问题
是有限的解空间的引进，其中包括一个
最佳解决方案。本文提出了这样一个解决方案空间
每个包装的代表由一对模块的名称序列，
被称为序列对。通过模拟搜索这个空间
退火，数百个模块已挤满有效地
证明。对于超大规模集成电路布局中的应用，我们攻击
最大的MCNC基准ami49与传统的布线面积
估计方法，并获得一个非常有前途的安置。
-Oracle cloud computing strategy to provide private and public clouds are two solutions for customers to choose to provide a comprehensive, integrated SaaS, PaaS, and IaaS products allow customers to cloud the minimum area rectangle based on business needs. Due to a variety of packaging is uncountable infinite, the successful optimization of the key problems is the introduction of a limited solution space, including a best solution. This paper presents such a solution space for each package on behalf of the name of the module by a pair of sequences, known as the sequences. Simulated search space annealing, hundreds of modules have been packed with proven effective. For applications in VLSI layout, we attack the largest MCNC benchmark ami49 with traditional wiring area estimation method, and a very promising placement.
Platform: |
Size: 692224 |
Author: jame |
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Description: 版图设计技术，超大规模集成电路，ASIC集成电路等课程知识，涵盖版图设计过程、前期准备工作、常用编辑软件、CMOS IC等.-Layout techniques, VLSI, ASIC integrated circuits and other curriculum knowledge, covering the territory of the design process, the preparatory work, commonly used editing software, CMOS IC and so on.
Platform: |
Size: 1981440 |
Author: yoyo |
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Description: Tanner Pro 集成电路设计与布局实战指导
本书根据作者三年多来教授 VLSI 设计实习的心得，编写的实例符合初学者的学习要求，
使学生能明了完整的设计流程。 -Tanner Pro IC design and layout of the actual guidance
This book more than a professor VLSI design internship experience three years according to the authors, examples written in compliance with the requirements for beginners to learn,
Enable students to understand the complete design process.
Platform: |
Size: 3616768 |
Author: xy |
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