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[Other resource] vspi

Description: verilog VSIP core,用verilog语言编写，希望对各位朋友有所帮助！
Platform: | Size: 13427 | Author: liuzinan | Hits:

[Other resource] vspi

Description: SPI的verilog实现，非常的全面和详细，还带有spi算法的注解！
Platform: | Size: 7011 | Author: 王和国 | Hits:

[Other resource] vspi

Description: spi总线控制器，包含vhdl和verilog两种代码方式来实现。
Platform: | Size: 13415 | Author: wangdong | Hits:

[VHDL-FPGA-Verilog] vspi

Description: verilog VSIP core,用verilog语言编写，希望对各位朋友有所帮助！-verilog VSIP core, using Verilog language, and they hope to help all our friends!
Platform: | Size: 13312 | Author: liuzinan | Hits:

[VHDL-FPGA-Verilog] vspi

Description: SPI的verilog实现，非常的全面和详细，还带有spi算法的注解！-SPI s Verilog realization, very comprehensive and detailed, but also with the annotation algorithm spi!
Platform: | Size: 7168 | Author: 王和国 | Hits:

[Embeded-SCM Develop] vspi_VHDL

Description: FPGA/CPLD VHDL语言实现SPI，拥有两种模式，FPGA/CPLD即可工作在主机模式，又可工作在从机模式 -FPGA/CPLD VHDL language SPI, have the two models, FPGA/CPLD can work in host mode, but also work in slave mode
Platform: | Size: 248832 | Author: 张焱 | Hits:

[VHDL-FPGA-Verilog] vspi

Description: spi总线控制器，包含vhdl和verilog两种代码方式来实现。-spi bus controller, including VHDL and Verilog code in two ways to achieve.
Platform: | Size: 13312 | Author: wangdong | Hits:

[VHDL-FPGA-Verilog] SPIsend

Description: Verilog HDL的程式，上網找到SPI程式， vspi.v這程式相當好用可用來接收與傳送SPI，並且寫了一個傳輸信號測試，spidatasent.v這程式就是傳送的資料，分別為00 66... 01 77...... 02 55這樣的資料，並透過MAX+PULS II軟體進行模擬，而最外層的程式是test_createspi.v！-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v!
Platform: | Size: 145408 | Author: Rick | Hits:

[VHDL-FPGA-Verilog] vspi

Description: 一个用vhdl语言写的spi接口实例，经过altera的fpga测试可以使用。-Written in a language with vhdl spi interface to an instance, after the fpga altera test can be used.
Platform: | Size: 6144 | Author: tofly | Hits:

[VHDL-FPGA-Verilog] l1ghVhVI

Description: The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
Platform: | Size: 226304 | Author: aaa | Hits:

[VHDL-FPGA-Verilog] vspi_rx_jiance

Description: 对VSPI的仿真，很详尽的仿真 明白如何利用vspi-vspi
Platform: | Size: 3840000 | Author: wangyang | Hits:

[VHDL-FPGA-Verilog] vspi

Description: 通用异步串行通信协议 SPI模块 VHLD语言 -SPI module
Platform: | Size: 6144 | Author: xuyi | Hits:

[VHDL-FPGA-Verilog] vspi

Description: SPI的Verilog实现带有SPI算法的注解-The implement of spi using Verilog HDL
Platform: | Size: 7168 | Author: guorui | Hits:

[VHDL-FPGA-Verilog] vspi

Description: VSPI special module with included docs
Platform: | Size: 13312 | Author: xornonop | Hits:

[VHDL-FPGA-Verilog] vspi

Description: 比较好的一个FPGA的spi总线核-Better FPGA spi bus nuclear 。。。
Platform: | Size: 3433472 | Author: 林子 | Hits:

[Other] vspi.v

Description: 实现SPI接口功能, 语言是verilog
Platform: | Size: 7168 | Author: jim | Hits:

[Other] vspi

Description: // Serial Peripheral Interface (SPI) // The VSPI core implements an SPI interface compatible with the many // serial EEPROMs, and microcontrollers. The VSPI core is typically used // as an SPI master, but it can be configured as an SPI slave as well. // -// Serial Peripheral Interface (SPI) // // The VSPI core implements an SPI interface compatible with the many // serial EEPROMs, and microcontrollers. The VSPI core is typically used // as an SPI master, but it can be configured as an SPI slave as well. // // The SPI bus is a 3 wire bus that in effect links a serial shift // register between the "master" and the "slave". Typically both the // master and slave have an 8 bit shift register so the combined // register is 16 bits. When an SPI transfer takes place, the master and // slave shift their shift registers 8 bits and thus exchange their 8 // bit register values. //
Platform: | Size: 7168 | Author: william | Hits:

[Other] vspi

Description: SPI串口的内核实现verilog语言和VHDL语言-The serial peripheral interface spi bus
Platform: | Size: 6144 | Author: david | Hits:

[Other] vSPI-master

Description: Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
Platform: | Size: 3336192 | Author: d.pershin | Hits:

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