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[Other resource] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 1956 | Author: 夏虫 | Hits:

[Other resource] modulewdt

Description: 用verilog语言编写的看门狗模块modulewdt-verilog language with the watchdog module modulewdt
Platform: | Size: 3140 | Author: 谢迪 | Hits:

[Other resource] watchdog.tar

Description: verilog编写的watchdog代码!请参考！
Platform: | Size: 2311 | Author: 刘志刚 | Hits:

[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[VHDL-FPGA-Verilog] watch2

Description: vhdl实现watchdog，在逻辑中可以加入本模块，实现看门狗。-VHDL achieve watchdog, the logic of the modules can be added to achieve watchdog.
Platform: | Size: 1024 | Author: | Hits:

[Other Embeded program] modulewdt

Description: 用verilog语言编写的看门狗模块modulewdt-verilog language with the watchdog module modulewdt
Platform: | Size: 3072 | Author: 谢迪 | Hits:

[VHDL-FPGA-Verilog] watchdog.tar

Description: verilog编写的watchdog代码!请参考！-Verilog code watchdog prepared! please refer to!
Platform: | Size: 2048 | Author: 刘志刚 | Hits:

[Embeded-SCM Develop] watch_dog

Description: 看门狗的verilog源代码，项目的一部分，绝对正确，测试通过。-Watchdog of the Verilog source code, part of the project, is absolutely correct, the test.
Platform: | Size: 1024 | Author: WangYong | Hits:

[Software Engineering] watchver

Description: watchdog with verilog
Platform: | Size: 141312 | Author: Y.D. chang | Hits:

[VHDL-FPGA-Verilog] watch_dog_rtl_source

Description: Watchdog timer verilog RTL code
Platform: | Size: 10240 | Author: Chris | Hits:

[VHDL-FPGA-Verilog] watchdog

Description: 看门狗定时器Verilog源码；用于MCU的辅助模块，定时特定的时间来做硬件复位，是用于避免固件跑死的一个机制。-Watchdog verilog source.
Platform: | Size: 4096 | Author: 郑佛少 | Hits:

[Static control] LIP1701CORE_system_watchdog

Description: System watchdog verilog code
Platform: | Size: 287744 | Author: jc | Hits:

[Other Embeded program] VMD642_CPLD

Description: 本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。-This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.
Platform: | Size: 48128 | Author: ye | Hits:

[Linux driver] watchdog

Description: 针对低功耗和低频率的看门狗设计verilog代码-watch dog design code
Platform: | Size: 2048 | Author: 冰人 | Hits:

[VHDL-FPGA-Verilog] watch_dog

Description: 看门狗程序设计，使用verilog HDL语言编写-Watchdog program design, using verilog HDL language
Platform: | Size: 1024 | Author: 甄红欣 | Hits:

[Embeded-SCM Develop] watch_dog

Description: 看门狗的verilog源代码，项目的一部分，绝对正确，测试通过。-Watchdog of the Verilog source code, part of the project, is absolutely correct, the test.
Platform: | Size: 1024 | Author: equences | Hits:

[VHDL-FPGA-Verilog] DW_apb_wdt

Description: verilog实现watch dog，可直接用于芯片开发中。-erilog realization watchdog, can be directly used for chip development.
Platform: | Size: 1801216 | Author: 刘精轶 | Hits:

[Program doc] dw_apb_wdt_db

Description: verilog实现watchdog参考文档，可用于实现watchdog。-verilog realize watchdog reference documentation can be used to implement the watchdog.
Platform: | Size: 732160 | Author: 刘精轶 | Hits:

[VHDL-FPGA-Verilog] multi_cpu

Description: 主要功能包含： // 1.按照CPU小系统规范要求，实现了各寄存器的读、写、控制等功能 // 2.实现了部分CPU读取配置字功能 // 3.实现了看门狗功能 // 4.实现了FLASH和BOOTROM控制功能 // 5.其它用户功能（按需进行添加）(The main functions include: According to the 1. / / CPU small system specifications, the realization of the register read and write control functions 2. / / achieve a part of the CPU configuration word read function 3. / achieve a watchdog function 4. / / FLASH and achieve a BOOTROM control function 5. / other user function (on-demand add))
Platform: | Size: 6144 | Author: fengyuanzyt | Hits:

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