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[VHDL-FPGA-Verilog] streamcipherbyvhdl

Description: describe the vlsi implementation of some stream cipher (RC4,A5/1,helix,E0)
Platform: | Size: 134144 | Author: hesham | Hits:

[VHDL-FPGA-Verilog] rc4

Description: RC4算法，WEP算法，加解密，密钥长度256-RC4 algorithm, WEP algorithm, encryption and decryption
Platform: | Size: 3072 | Author: shixu | Hits:

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