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[Other resource] Wishbone DL : 0: wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical description of the text block!
Update : 2008-10-13 Size : 1.28mb Publisher : bluewind
[Documents] WISHBONE中文版 DL : 0: 片上总线协议WISHBONE B4中文版，帮助英文不是很好的同学快速学习这个总线协议
Update : 2011-11-22 Size : 312kb Publisher : luoxp96@163.com
[Books] wbspec_b3 DL : 0: soc中ip核集成时所采用的一种片上总线，开发的，为opencores所采用，wishbone片上总线指南-were integrated ip nuclear adopted by an on-chip bus, development, for opencores using the on-chip bus wishbone Guide
Update : 2025-02-17 Size : 767kb Publisher : 钱丰勇
[SCM] Wishbone DL : 0: wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical description of the text block!
Update : 2025-02-17 Size : 1.28mb Publisher :
[VHDL-FPGA-Verilog] wb_conbus.tar DL : 0: wishbone 源代码，opencore-wishbone source code, opencore
Update : 2025-02-17 Size : 15kb Publisher : 姚卫忠
[VHDL-FPGA-Verilog] wishbone_i2c_master DL : 0: -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
Update : 2025-02-17 Size : 5kb Publisher : 郑开科
[VHDL-FPGA-Verilog] adma DL : 0: Wishbone dma ip core
Update : 2025-02-17 Size : 7kb Publisher : liwen
[Com Port] simple_spi DL : 0: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Update : 2025-02-17 Size : 462kb Publisher : Jack
[Other] PCI_Bridge_Guest_UART DL : 0: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Update : 2025-02-17 Size : 8.04mb Publisher : heartbeat
[ELanguage] rs232_syscon_v DL : 0: This a state-machine driven rs232 serial port interface to a "Wishbone" // type of bus.-This a state-driven machine rs232 seria l port interface to a "Wishbone"// type of bus.
Update : 2025-02-17 Size : 11kb Publisher : weixing
[Com Port] wishbone_i2c_master_vhd DL : 0: WISHBONE revB2 compiant I2C master core
Update : 2025-02-17 Size : 5kb Publisher : weixing
[MiddleWare] opencores_i2c_master DL : 0: i2c VHDL,能够实现I2C 用的是wishbone总线
Update : 2025-02-17 Size : 189kb Publisher : wang
[Software Engineering] Wishbone_from_opencores DL : 0: 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。-This is collected in OPENCORE Wishbone bus and guide the development of note, with the electronic design of a large number of open source IP applications, wishbone bus is also becoming increasingly popular.
Update : 2025-02-17 Size : 817kb Publisher : 刘庆强
[matlab] OptimizationofaDoubleWishboneSuspensionSystem DL : 0: This demo shows how to use MATLAB, Optimization Toolbox, and Genetic Algorithm and Direct Search Toolbox to optimize the design of a double wishbone suspension system.
Update : 2025-02-17 Size : 1.96mb Publisher : 阳关
[VHDL-FPGA-Verilog] SoC_WishboneSystem DL : 0: SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Update : 2025-02-17 Size : 89kb Publisher : 周华茂
[VHDL-FPGA-Verilog] opb_wb DL : 0: 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信，从而使用基于Wishbone的许多开源IP Core-This is a Wishbone Bus connectivity OPB and the Bridge, that allows OPB and the Wishbone Bus to connect the open source communications, and thus the use of Wishbone s many open-source-based IP Core
Update : 2025-02-17 Size : 23kb Publisher : 古月
[Embeded-SCM Develop] The_Analyse_And_Research_of_embeded_SoC_Bus DL : 0: 本文主要介绍和分析了在集成芯片设计中几种常用的片上系统总线－CoreConnect 总线、MBA 总线、Wishbone 总线和OCP 总线，通过比较这些总线的特性及适用范围，展望了它们的发展前景。-This paper introduces and analyzes the design of integrated chips in several commonly used system-on-chip bus-CoreConnect Bus, MBA Bus, Wishbone bus and OCP bus, by comparing the characteristics of these bus, and the scope of application and look forward to their prospects for development.
Update : 2025-02-17 Size : 167kb Publisher : wsj
[VHDL-FPGA-Verilog] wisbone_2_ahb.tar DL : 0: ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.--------- ---- WISHBONE Wishbone_BFM IP Core---- -------- ---- This file is part of the Wishbone_BFM project---- ---- http://www.opencores.org/cores/Wishbone_BFM/---- -------- ---- Description---- ---- Implementation of Wishbone_BFM IP core according to---- ---- Wishbone_BFM IP core specification document.
Update : 2025-02-17 Size : 2.66mb Publisher : liang
[VHDL-FPGA-Verilog] wb_rtc DL : 0: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Update : 2025-02-17 Size : 8kb Publisher : 姓名
[VHDL-FPGA-Verilog] wishbone DL : 0: wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
Update : 2025-02-17 Size : 13kb Publisher : thegreeneyes

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