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[Other resource] wb_conbus.tar

Description: wishbone 源代码，opencore-wishbone source code, opencore
Platform: | Size: 14905 | Author: 姚卫忠 | Hits:

[VHDL-FPGA-Verilog] wb_conbus.tar

Description: wishbone 源代码，opencore-wishbone source code, opencore
Platform: | Size: 15360 | Author: 姚卫忠 | Hits:

[VHDL-FPGA-Verilog] SoC_WishboneSystem

Description: SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 91136 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] SoCWishboneSystem

Description: SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
Platform: | Size: 90112 | Author: 肖冠兰 | Hits:

[VHDL-FPGA-Verilog] wishbone_VHDL

Description: wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
Platform: | Size: 464896 | Author: 王鹏 | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[VHDL-FPGA-Verilog] ahb2wishbone_latest.tar

Description: AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
Platform: | Size: 10640384 | Author: rex | Hits:

[Compress-Decompress algrithms] ahb2wishbone_latest.tar

Description: AHB to Wishbone memory interface VHDL source code
Platform: | Size: 10638336 | Author: cyf | Hits:

[VHDL-FPGA-Verilog] IIC_verilog

Description: IIC控制器，源代码verilog,WISHBONE总线-IIC controllers, the source code verilog
Platform: | Size: 11264 | Author: 晨光 | Hits:

[VHDL-FPGA-Verilog] uart16550_latest.tar

Description: UART16550是16550兼容的UART核心（主要）。 总线接口是WISHBONE SoC总线启。B. 所有功能的标准选择16550 UART：FIFO的基础操作，要求和其他中断。 数据表可以下载从CVS树随着源代码-uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded the CVS tree along with the source code
Platform: | Size: 1545216 | Author: asdtgg | Hits:

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