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Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descripted in the Constrained file quad.ucf.
To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.
For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descripted in the Constrained file quad.ucf.
To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.
For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
Platform: |
Size: 70656 |
Author: JUPP |
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Description: Project frequency inverter for induction motors very helpful
Platform: |
Size: 52224 |
Author: Arao |
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Description: Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl
Platform: |
Size: 1024 |
Author: Arao |
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Description: 根据中等容量感应电机空间矢量控制的特点,设计了一种基于16位定点数字信号处理器TMS320F240和复杂可编程逻辑器件XC9536的矢量控制系统,并详细说明了其软硬件设计方法。实验结果表明,该控制系统充分利用了TMS320F240和XC9536的硬件资源和特点,软硬件设计合理、实时性较好,能可靠完成空间矢量控制算法。
(According to the characteristics of medium-power induction motor vector control,a controlling system based on
16-bit fixed point digital signal processor(DSP) TMS320F240 and complex programmable logic device(CPLD) XC9536 is designed in this paper,and the design method of software and hardware is described in detail.The experimental results show that the controlling system takes full advantages of the characteristics and the hardware resources of TMS320F240 and XC9536,has a well designed software and hardware structures and a good real-time
performance,and is complete in complicated space vector calculation.
)
Platform: |
Size: 48128 |
Author: 芃芃其麦 |
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