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[VHDL-FPGA-Verilogxilinx_iic_spi

Description: xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface
Platform: | Size: 1765376 | Author: 杨子树 | Hits:

[VHDL-FPGA-Verilogpicoblaze_pwm_control

Description: 基于Xilinx的8位软核PicoBlaze的Pwm设计,采用汇编语言设计。使用软件模拟spi接口-Based on the Xilinx PicoBlaze soft-core 8-bit design of Pwm, using assembly language design. Spi interface with software simulation
Platform: | Size: 675840 | Author: 扑天雕 | Hits:

[assembly languageSPI-Core_nguyen

Description: SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE.STD_LOGIC_1164 IEEE.NUMERIC_STD work.general_signal_processing_pkg (included) Testbench for simulation included. Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
Platform: | Size: 17408 | Author: AgentNguyex | Hits:

[Technology Managementaxi_spi_ds742

Description: xilinx,microblaze的spi ip核的datasheet。xilinx官网速度慢,分享给有需要的朋友。 -xilinx, microblaze the spi ip core datasheet. xilinx Officer slow speed of network share to a friend in need.
Platform: | Size: 445440 | Author: sol | Hits:

[Otherxapp800

Description: XAPP800SPICPLD源码参考设计-THIS DESIGN IS PROVIDED TO YOU AS IS . XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design should be used only as an example design, not as a fully functional core. XILINX does not warrant the performance, functionality, or operation of this Design will meet your requirements, or that the operation of the Design will be uninterrupted or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant or make any representations regarding use or the results of the use of the Design in terms of correctness, accuracy, reliability or otherwise. THIRD PARTIES INCLUDING MOTOROLA MAY HAVE PATENTS ON THE SERIAL PERIPHERAL INTERFACE ( SPI ) BUS. BY PROVIDING THIS HDL CODE AS ONE POSSIBLE IMPLEMENTATION OF THIS STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THE PR
Platform: | Size: 396288 | Author: 杜维忠 | Hits:

[VHDL-FPGA-Verilogflash_spi_master_axi

Description: 使用xilinx 的QUAD spi core 对flash芯片进行控制的代码。-Using xilinx s Quad SPI core to control the external flash device.
Platform: | Size: 6144 | Author: 陈剑冰 | Hits:

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