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[Other resource] pwm1

Description: xilinx设计并完成一个10位的D/F转换器，输入的数字量分别由按键K1,K2来调节，其中K1完成加1功能，而K2则完成减1功能，并把转换的结构西哦女冠到BUZZ蜂鸣器上。
Platform: | Size: 79450 | Author: haolj | Hits:

[Other resource] Fibonacci_sequence

Description: 用MATLAB 里的XILINX BLOCKS编写, 实现Fibonacci sequence算法, 当F为0时, 输出为0 F为1时, 输出为1 当F为N 时, 输出为F的N-1 加上 F的N-2.
Platform: | Size: 25685 | Author: zhang tian | Hits:

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

Description: xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
Platform: | Size: 1432576 | Author: ningchang | Hits:

[VHDL-FPGA-Verilog] pwm1

Description: xilinx设计并完成一个10位的D/F转换器，输入的数字量分别由按键K1,K2来调节，其中K1完成加1功能，而K2则完成减1功能，并把转换的结构西哦女冠到BUZZ蜂鸣器上。-Xilinx design and complete a 10-bit D/F converter, the digital input from the keys K1, K2 to regulate, including the completion of plus 1 functions K1, K2 and completed by 1 functions, and to convert the structure of the West Oh F BUZZ crown to the buzzer on.
Platform: | Size: 79872 | Author: haolj | Hits:

[VHDL-FPGA-Verilog] Fibonacci_sequence

Description: 用MATLAB 里的XILINX BLOCKS编写, 实现Fibonacci sequence算法, 当F为0时, 输出为0 F为1时, 输出为1 当F为N 时, 输出为F的N-1 加上 F的N-2.-Using MATLAB in the XILINX BLOCKS prepared realize Fibonacci sequence algorithm, when F is 0, the output for 0 F for one, the output is 1 when F is N, the output for the F of the N-1 plus F of N-2 .
Platform: | Size: 25600 | Author: zhang tian | Hits:

[VHDL-FPGA-Verilog] Mars-SP3-U_FPGA_manual

Description: Mars-SP3-U FPGA开发板说明，针对Xilinx的XC3S400，有对原理图的说明和实例操作说明-Mars-SP3-U FPGA development board that Xilinx for the XC3S400, there is schematic diagram of the description and examples of instructions
Platform: | Size: 645120 | Author: iversn | Hits:

[VHDL-FPGA-Verilog] reload_fir

Description: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Platform: | Size: 16727040 | Author: 林寒风 | Hits:

[VHDL-FPGA-Verilog] I2C_control

Description: Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ******************************************************************************************************************************************** ******************************************************************************************************************************************** File Contents ******************************************************************************************************************************************** This zip file contains the following folders: \doc -- Document for the CoolRunner I2C Controller. \exemplar -- Exemplar synthesis files. This design was synthesized using Exemplar and the resulting EDIF file imported into XPLA Professional V3.22 \vhdl_source -- Source VHDL files: i2c.vhd - top level file i2c_control.vhd - control function for the I2C master/slave shift.vhd - shift register uc_interface.vhd- uC interface f
Platform: | Size: 150528 | Author: leon | Hits:

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