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[Other resource] xapp935 DL : 0: ddr2 controller, verilog source code from xilinx
Update : 2008-10-13 Size : 338.87kb Publisher : Hubert
[Other resource] Xil3SD1800A_MIG_ISIM_vlog_v92 DL : 0: Xilinx DDR2存储器接口调试代码，主频167Mhz，嵌入了CHIPSCORP代码。
Update : 2008-10-13 Size : 3.23mb Publisher : king523103@163.com
[VHDL-FPGA-Verilog] xapp935 DL : 0: ddr2 controller, verilog source code from xilinx
Update : 2025-02-17 Size : 339kb Publisher : Hubert
[VHDL-FPGA-Verilog] FPGAdesignXilinx DL : 0: 华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。-Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.
Update : 2025-02-17 Size : 1.63mb Publisher : 高超
[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_ISIM_vlog_v92 DL : 0: Xilinx DDR2存储器接口调试代码，主频167Mhz，嵌入了CHIPSCORP代码。-Xilinx DDR2 memory interface debug code, frequency 167Mhz, embedded code CHIPSCORP.
Update : 2025-02-17 Size : 3.23mb Publisher : king523103@163.com
[Embeded-SCM Develop] amp DL : 0: 本资料主要是Xilinx对于DDR2的IP核的一个简单应用-This information is Xilinx' s IP for DDR2 a simple application of nuclear
Update : 2025-02-17 Size : 64kb Publisher : 易
[VHDL-FPGA-Verilog] ddr2 DL : 0: 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Update : 2025-02-17 Size : 2.66mb Publisher : Zhao Bill
[VHDL-FPGA-Verilog] s3ask_ddr2 DL : 0: DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
Update : 2025-02-17 Size : 2.49mb Publisher : Joe Zhu
[VHDL-FPGA-Verilog] c_xapp260 DL : 0: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Update : 2025-02-17 Size : 1.07mb Publisher : 陈阳
[VHDL-FPGA-Verilog] c_xapp454 DL : 0: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Update : 2025-02-17 Size : 212kb Publisher : 陈阳
[VHDL-FPGA-Verilog] c_xapp858 DL : 0: 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the interface used to achieve high-performance DDR2 SDRAM controller and data acquisition technology. This data collection technique used in each Virtex ™ -5 I/O has an input serializer/deserializer (ISERDES) and output double data rate (ODDR) function.
Update : 2025-02-17 Size : 437kb Publisher : 陈阳
[VHDL-FPGA-Verilog] mcb_read_write DL : 0: 赛灵思 DDR2 用户接口程序原创。希望对各位有用。-Xilinx DDR2 original user interface program. You want to be useful.
Update : 2025-02-17 Size : 2kb Publisher : wenchunhong
[Other] c_xapp702 DL : 0: 介绍用xilinx VIRTEX4系列器件实现DDR2控制-Introduction to use xilinx VIRTEX4 control devices to achieve DDR2
Update : 2025-02-17 Size : 277kb Publisher : zhanghua
[VHDL-FPGA-Verilog] ml505_mig_design DL : 0: Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
Update : 2025-02-17 Size : 8.9mb Publisher : 黑羽·X
[VHDL-FPGA-Verilog] spartan6 DL : 0: xilinx spartan-6 fpga原理图，包括电源部分，外接ddr2等功能 -xilinx spartan-6 fpga schematics, including power supply, external features such as ddr2
Update : 2025-02-17 Size : 304kb Publisher : 刘一平
[VHDL-FPGA-Verilog] DDR2PTiming DL : 0: 用Xilinx ip core 生成器所产生的DDR2控制器，进行时序分析代码-Xilinx ip core generator a ddr2 controllor time analysis
Update : 2025-02-17 Size : 4kb Publisher : huangning
[VHDL-FPGA-Verilog] ~DDR2-Demonstration DL : 0: 基于Xilinx-FPGA的DDR2演示代码-DDR2 Reference design which Based on Xilinx-FPGA
Update : 2025-02-17 Size : 2.71mb Publisher : saladin
[VHDL-FPGA-Verilog] ddr2 DL : 0: 基于xilinx spartan -3A DSP的ddr2控制器-Based on the Xilinx Spartan-3A DSP DDR2 controller
Update : 2025-02-17 Size : 11.57mb Publisher : 朱义
[VHDL-FPGA-Verilog] ddr2 DL : 0: xilinx ddr2 mig核读写控制 verilog -xilinx mig write and read timing
Update : 2025-02-17 Size : 7.92mb Publisher : yoek
[Software Engineering] DDR2-User-Interface-PPT DL : 0: design of DDR2 with Xilinx
Update : 2025-02-17 Size : 51kb Publisher : rohit

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