Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - xilinx fpga fir

Search list

[Software Engineering] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228801 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228352 | Author: yaoming | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[matlab] filter

Description: 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
Platform: | Size: 268288 | Author: xueanxi | Hits:

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

Description: FIR filter design method using Xilinx FPGA platform.
Platform: | Size: 1805312 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] reload_fir

Description: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Platform: | Size: 16727040 | Author: 林寒风 | Hits:

[VHDL-FPGA-Verilog] fenbushisuanfa

Description: 分布式算法在20多年前被首次提出，但直到Xilinx发明FPGA的查找表结构以后，分布式算法才在20世纪90年代初重新受到重视，并被有效地应用在FIR滤波器的设计中。 分布式算法是基于查找表的一种计算方法，在利用FPGA实现数字信号处理方面发挥着重要的作用，可以大大提高信号的处理效率。它主要应用于数字滤波、频率转换等数字信号处理的乘累加运算。 -see up
Platform: | Size: 112640 | Author: 张锴 | Hits:

[VHDL-FPGA-Verilog] Xilinx-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Platform: | Size: 3090432 | Author: 胡文静 | Hits:

[VHDL-FPGA-Verilog] fir_test

Description: 采用xilinx进行的FPGA的FIR滤波器设计-Conducted using xilinx FPGA FIR filter design
Platform: | Size: 1033216 | Author: 张兴 | Hits:

[VHDL-FPGA-Verilog] filter_2d

Description: XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
Platform: | Size: 1642496 | Author: gsp | Hits:

[Software Engineering] DSP-with-FPGAs

Description: Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, to name just a few, previously built with ASICs or PDSPs, are now most often replaced by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains (Xilinx Virtex, Altera FLEX) that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs [1]. Previous FPGA families have most often targeted TTL “glue logic” and did not have the high gate count needed for DSP functions. The efficient implementation of these front-end algorithms is the main goal of this book.
Platform: | Size: 8656896 | Author: Alexander | Hits:

[VHDL-FPGA-Verilog] FPGA-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码
Platform: | Size: 3090432 | Author: 楚轩 | Hits:

[Other] 7875-35453-1-PB

Description: FIR polyphase XILINX FPGA article
Platform: | Size: 2295808 | Author: Temer | Hits:

[Other] Comparative study of FFA architectures using different multiplier and adder topologies

Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Platform: | Size: 1123027 | Author: nalevihtkas | Hits:

CodeBus www.codebus.net