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Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.
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Size: 899078 |
Author: lee |
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Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.-PCI Design Guide The Xilinx LogiCORE PCI interface is a fully verified, pre-implementedPCI Bus interface. This interface is available in 32-bit and 64-bit versions, with support for multiple Xilinx FPGA device families. Itis designed to support both Verilog-HDL and VHDL. The designexamples in this book are provided in Verilog.
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Size: 899072 |
Author: lee |
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Description: xapp997 from xilinx, not so easy to find: an USB application for the Logicore USB core
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Size: 1699840 |
Author: bugidan |
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Description: AWGN Xilinx Logicore
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Size: 585728 |
Author: mojtaba |
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Description: 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。
2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。
3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据，DA数据。
4， DriverStudio生成的驱动代码，最大限度的提高连续传输的速率，同时降低PC的负载。
5， 用户自定义BAR2空间，可用作自定义控制。
6， 支持32位和64位操作系统。
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Size: 2329600 |
Author: rosen |
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Description: The Xilinx Video Scaler LogiCORE™ IP is an optimized
hardware block that converts an input color image of
one size to an output image of a different size. This
highly configurable core supports in-system
programmability on a frame basis. System design is
made easier through support of both streaming-video
and frame buffer-based interfaces. This core is designed
to connect via an AXI4-Lite interface.-The Xilinx Video Scaler LogiCORE™ IP is an optimized
hardware block that converts an input color image of
one size to an output image of a different size. This
highly configurable core supports in-system
programmability on a frame basis. System design is
made easier through support of both streaming-video
and frame buffer-based interfaces. This core is designed
to connect via an AXI4-Lite interface.
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Size: 1171456 |
Author: JackTong |
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Description: 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值
-The LogiCORE IP AXI Timer/Counter is a 32/
64-bit timer module that interfaces to the
AXI4-Lite interface.
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Size: 434176 |
Author: bill zhao |
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