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[VHDL-FPGA-Verilog] xilnx_sata DL : 0: xilinx 的sata解决方案，已对其中内容作了修改，可实现综合-sata the xilinx solutions have been made to amend the contents of which can be used
Update : 2025-02-17 Size : 64kb Publisher : 张峰
[VHDL-FPGA-Verilog] jpeg_hardware.tar DL : 0: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co
Update : 2025-02-17 Size : 848kb Publisher :