Search - xilinx serial vhdl

[Other resource] myUART

Description: 这是我用Xilinx公司的sparten3开发板,ISE集成开发环境，用VHDL语言开发的串口全双工通信程序，供大家参考，共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for your reference, learning together.
Platform: | Size: 657416 | Author: 汪莉莉 | Hits:

[Other resource] xapp355

Description: Serial ADC Interface write in VHDL based on xilinx cpld
Platform: | Size: 34080 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] uart_vhdl_xilinx

Description: xilinx的串口仿真程序-xilinx simulator programme of serial port
Platform: | Size: 9216 | Author: 赵兴涛 | Hits:

[VHDL-FPGA-Verilog] USBXilinx

Description: 实现了串行通信接口的全部功能，符合RS-232-C标准的完整UART模块源代码，中文注解，清晰易懂，经过严格仿真测试，绝对好用。-a serial communication interface of all functions, with RS-232-C standard UART modules complete source code, Chinese notes, lucid, after a rigorous simulation tests, absolutely useful.
Platform: | Size: 462848 | Author: 张海 | Hits:

[VHDL-FPGA-Verilog] myUART

Description: 这是我用Xilinx公司的sparten3开发板,ISE集成开发环境，用VHDL语言开发的串口全双工通信程序，供大家参考，共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for your reference, learning together.
Platform: | Size: 657408 | Author: 汪莉莉 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Platform: | Size: 2048 | Author: ronghy | Hits:

[Other Embeded program] RS232

Description: 基于XILINX的内嵌POWERPC的处理器的串行通讯的应用源代码.-XILINX PowerPC-based embedded processor serial communication application source code.
Platform: | Size: 344064 | Author: 王晶 | Hits:

[Embeded-SCM Develop] high-speed-serialIO

Description: 高速串行IO方面的一本电子书，是xilinx公司发布的，认为相当不错，供大家一起学习-High-speed serial IO aspects of an e-book is issued by Xilinx Inc., consider pretty good for everyone to learn
Platform: | Size: 1708032 | Author: cao | Hits:

[VHDL-FPGA-Verilog] xapp355

Description: Serial ADC Interface write in VHDL based on xilinx cpld
Platform: | Size: 33792 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] I2C

Description: I2C 串口通讯Xilinx项目源码拷贝到硬盘，用ISE打开工程文件即可。-I2C Serial Communication Xilinx source project are copied to the hard drive, using ISE project file can be opened.
Platform: | Size: 212992 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] aa

Description: xilinx环境下开发vhdl语言串行接口设计-Xilinx VHDL language development environment serial interface design
Platform: | Size: 219136 | Author: wang | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232串口通信协议，verilog实现，通过FPGA完全调通。-RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
Platform: | Size: 3072 | Author: dingsheng | Hits:

[Com Port] uart

Description: 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
Platform: | Size: 6144 | Author: zhangjiansen | Hits:

[Embeded-SCM Develop] This_is_pci-wishbone_nuclear_and_16450_serial_port

Description: 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
Platform: | Size: 8428544 | Author: iceskull | Hits:

[Software Engineering] FPGA_RS232

Description: 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction.
Platform: | Size: 215040 | Author: jalon | Hits:

[VHDL-FPGA-Verilog] Xilinx_3SE_Starter_Serial_Flash_v91

Description: sparntan 3e中基于串行flash的读写操作-sparntan 3e serial flash-based reading and writing
Platform: | Size: 905216 | Author: zyb | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述第2章 Verilog HDL基础与开发平台操作指南第3章 Verilog HDL程序结构第4章 VERILOG HDL语言基本要素第5章面向综合的行为描述语句第6章面向验证和仿真的行为描述语句第7章系统任务和编译预处理语句第8章 VERILOG HDL可综合设计的难点解析第9章高级逻辑设计思想与代码风格第10章可综合状态机开发实例第11章常用逻辑的VERILOG HDL实现第12章 XILINX硬核模块的VERILOG HDL调用第13章串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27825152 | Author: lyy | Hits:

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[Other resource] myUART

[Other resource] xapp355

[VHDL-FPGA-Verilog] uart_vhdl_xilinx

[VHDL-FPGA-Verilog] USBXilinx

[VHDL-FPGA-Verilog] myUART

[VHDL-FPGA-Verilog] RS232

[Other Embeded program] RS232

[Embeded-SCM Develop] high-speed-serialIO

[VHDL-FPGA-Verilog] xapp355

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] aa

[VHDL-FPGA-Verilog] RS232

[Com Port] uart

[Embeded-SCM Develop] This_is_pci-wishbone_nuclear_and_16450_serial_port

[Software Engineering] FPGA_RS232

[VHDL-FPGA-Verilog] Xilinx_3SE_Starter_Serial_Flash_v91

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart1

[VHDL-FPGA-Verilog] uart_rx

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